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2023-01-21sb/amd/pi/hudson/Kconfig: Remove AHCI_ROM_FILEElyes Haouas
Remove AHCI_ROM_FILE since it's not used and there is no ahci.bin file. Change-Id: I008c6ac78957500d4ce301fe70f5b6d4a549b573 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12treewide: Remove unused <cpu/x86/smm.h>Elyes Haouas
Change-Id: Iba5b39c6189d3224ba209c7985153701fe8896fb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09sb/intel/common/spi: Fix building for 64bitArthur Heymans
This avoids the warning of casting pointers to integers of different size. Change-Id: I7bcb6dbf286438115c854d618eaa2da21c81400d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69389 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-23sb/intel/lynxpoint: Add Kconfig option to hide Intel MEMatt DeVillier
On lynxpoint devices, coreboot currently disables and hides the ME PCI interface by default, without any way to opt out of this behavior. Add a Kconfig option to allow for leaving the ME PCI interface enabled, but set the default to disabled as to leave the current behavior unchanged. Change-Id: I994cb5b05829eddad2e423a7440a9458f9952370 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-12-23tree: Replace And(a,b) with ASL 2.0 syntaxFelix Singer
Replace `And (a, b)` with `a & b`. Change-Id: Id8bbd1a477e6286bbcb5fa31afd1c7a860b1c7dc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70851 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace Or(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Or (a, b, c)` with `c = a | b`, respectively `c |= b` where possible. Change-Id: Icf194b248075f290de90fb4bc4e9a0cd9d76ec61 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70846 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace ShiftLeft(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `ShiftLeft (a, b, c)` with `c = a << b`. Change-Id: Ibd25a05f49f79e80592482a1b0532334f727af58 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70841 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb,x86/smm: Disable unused IO trapsKyösti Mälkki
Only IO trap #3 for lenovo/x60,t60 and getac/p470 have implemented the IO trap handler. Change-Id: Ibadce174f673e88380f4b6745fd9ed8b73177a13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70367 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-16sb/intel/lynxpoint: Add native PCH initAngel Pons
Implement native PCH initialisation for Lynx Point. This is only needed when MRC.bin is not used. Change-Id: I36867bdc8b20000e44ff9d0d7b2c0d63952bd561 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-16sb/intel/lynxpoint: Add native thermal initAngel Pons
Implement native thermal initialisation for Lynx Point. This is only needed when MRC.bin is not used. Change-Id: I4a67a3092d0c2e56bfdacb513a899ef838193cbd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64180 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-16sb/intel/lynxpoint: Add native USB initAngel Pons
Implement native USB initialisation for Lynx Point. This is only needed when MRC.bin is not used. TO DO: Figure out how to deal with the FIXME's and TODO's lying around. Change-Id: Ie0fbeeca7b1ca1557173772d733fd2fa27703373 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-16haswell/lynxpoint: Add native early ME initAngel Pons
Implement native early ME init for Lynx Point. This is only needed when MRC.bin is not used. Change-Id: If416e2078f139f26b4742c564b70e018725bf003 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-16haswell/lynxpoint: Add native DMI initAngel Pons
Implement native DMI init for Haswell and Lynx Point. This is only needed on non-ULT platforms, and only when MRC.bin is not used. TEST=Verify DMI initialises correctly on Asrock B85M Pro4. Change-Id: I5fb1a2adc4ffbf0ebbf0d2d3a444055c53765faa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-15treewide: Remove unused 'include <arch/io.h>'Elyes Haouas
Change-Id: I6f1d7625eb457084ba893b25518fdfdb59cf64db Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-14sb/intel/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I94b2e6ecb90a2616e184ae9331c397c75089e373 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12sb/intel/common/acpi_pirq_gen.h: Fix conflicting types for ↵Elyes Haouas
'is_slot_pin_assigned' Found using 'Wenum-int-mismatch' (GCC-13: default with -Wall): src/southbridge/intel/common/acpi_pirq_gen.c:69:6: error: conflicting types for 'is_slot_pin_assigned' due to enum/integer mismatch; have 'bool(const struct slot_pin_irq_map *, unsigned int, unsigned int, enum pci_pin)' {aka '_Bool(const struct slot_pin_irq_map *, unsigned int, unsigned int, enum pci_pin)'} [-Werror=enum-int-mismatch] 69 | bool is_slot_pin_assigned(const struct slot_pin_irq_map *pin_irq_map, | ^~~~~~~~~~~~~~~~~~~~ In file included from src/southbridge/intel/common/acpi_pirq_gen.c:8: src/southbridge/intel/common/acpi_pirq_gen.h:91:6: note: previous declaration of 'is_slot_pin_assigned' with type 'bool(const struct slot_pin_irq_map *, unsigned int, unsigned int, unsigned int)' {aka '_Bool(const struct slot_pin_irq_map *, unsigned int, unsigned int, unsigned int)'} 91 | bool is_slot_pin_assigned(const struct slot_pin_irq_map *pin_irq_map, | ^~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors Change-Id: Ie91947d00feaae42314ec2d1291f39d667a85346 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70387 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-11sb/intel/common: Move definition of TRAPKyösti Mälkki
Both TRAP and TRP0 are now only defined for i82801gx ASL. This fixes an issue with updating to IASL 20221020, with many intel platform builds failing with: dsdt.asl 38: TRP0 = 0 Error 6084 - ^ Object does not exist (TRP0) The error was ignored with older IASL. Change-Id: Ie8a59803f4a27a8315c16bde401f8ca90ee814a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-10treewide: Include <device/mmio.h> instead of <arch/mmio.h>Elyes Haouas
<device/mmio.h>` chain-include `<arch/mmio.h>: https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes Also sort includes while on it. Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-09sb/intel/ibexpeak/Makefile.inc: Remove path to non-existent folderElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: I7c2217bbe677810d25c5d5d1062320773ee7e0c8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70386 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-09sb/intel/i82801jx/Makefile.inc: Remove path to non-existent folderElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: I2e69822575e42b322eb971540821f3b87fb7e903 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-07sb,soc/intel,mb: Drop leftover comments and TODOs in ASLKyösti Mälkki
Change-Id: I74f943e9b616458a16aa13c29706cf1551fcbbb2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-07mb,sb,soc/intel: Drop useless IO trap handlersKyösti Mälkki
There are four requirements for the SMI to hit a printk() this commit now removes. Build must have DEBUG_SMI=y, otherwise any printk() is a no-op inside SMM. ASL must have a TRAP() with argument 0x99 or 0x32 for SMIF value. Platform needs to have IO Trap #3 enabled at IO 0x800. The SMI monitor must call io_trap_handler for IO Trap #3. At the moment, only getac/p470 would meet the above criteria with TRAP(0x32) in its DSDT _INI method. The ASL ignores any return value of TRAP() calls made. A mainboard IO trap handler should have precedence over a southbridge IO trap handler. At the moment we seem to have no cases of the latter to support, so remove the latter. Change-Id: I3a3298c8d9814db8464fbf7444c6e0e6ac6ac008 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-07sb,soc/intel: Fix SMI handler IO trap data maskKyösti Mälkki
Shift is done in multiples of 8 (1 << 3) bits. It was fixed already for i82801ix/jx. Change-Id: I5e1c2b3bf4ba68f34eb43e59fe783d5cd6e0a39a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-06sb,soc/amd: Remove unused southbridge_io_trap_handler()Kyösti Mälkki
At the moment IO trap is not implemented for AMD platforms. Change-Id: Ib62ac4e4e418a8bab80c30dfb5183ecd8beb998d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06sb/intel/bd82x6x: Use {read,write}32pElyes Haouas
While on it, sort includes. Change-Id: Iacc858fbad89b54b1f5891c18cd3043b3963d53f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06sb/amd/pi/hudson: Use {read,write}16/32p()Elyes Haouas
Change-Id: Ic8621a18a1b3c299c3d6eb7b4bff39f1ff7d8492 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-05cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfmArthur Heymans
C5, C6 and slfm depend on the southbridge and the northbridge to be able to provide this functionality, with some just lacking the possibility to do so. Move the devicetree configuration to the southbridge. This removes the need for a magic lapic in the devicetree. Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-02sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}Elyes Haouas
Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70114 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-30/: Remove extra space after commaElyes Haouas
Change-Id: Ic64625bdaf8c4e9f8a5c1c22cece7f4070012da7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69903 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-28sb,soc/intel: Drop spurious SMI entry messageKyösti Mälkki
The message only makes sense if ACPI PM base address is allowed to be dynamic. If requested, it can be logged in common code. Change-Id: Iad7a60098c0391cc23384035af49e373dad90233 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-28sb/intel/common: Rename TCO timeoutKyösti Mälkki
Rename TCO1_TIMEOUT to TCO_TIMEOUT to match rest of the tree. Change-Id: Ib136e9b2d0006eb4ceceb298b557644760d1185c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-28sb,soc/intel: Address TCO SECOND_TO_STS name collisionKyösti Mälkki
Later soc/intel/common/smbus addresses TCO2_STS as a separate 16-bit register, while baytrail and braswell assumes 32-bit wide TCO1_STS to extend as TCO2_STS. In src/soc/intel/denverton_ns: #define TCO2_STS_SECOND_TO 0x02 In soc/intel/baytrail,braswell: #define SECOND_TO_STS (1 << 17) Elsewehere #define SECOND_TO_STS (1 << 1) It's expected that we remove the first (1 << 17) case and only access TCO2_STS as a separate 16-bit register. For now, use unique names to avoid confusion. Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-28sb,soc/intel: Apply transitional flag TCO_SPACE_NOT_YET_SPLITKyösti Mälkki
Tree is inconsistent with the use of TCO register space offsets and related preprocessor defines. The legacy space was offset from ACPI PM base by 0x60, but this changed with later platforms. The convenient way is to define the TCO registers relative to its base address and subtract 0x60 here, but this change cannot be easily done tree-wide or in one go. For the transient period, apply TCO_SPACE_NOT_YET_SPLIT flag until all platforms use a clean style of tco_{read,write} accessor functions instead of {read,write}_pmbase16(), or worse, inw/outl(). Change-Id: I16213cdb13f98fccb261004b31e81a9a44cb6e3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-28aopen/dxplplusu: Support SMM_ASEG and SMM_TSEGKyösti Mälkki
Both SMM_ASEG and SMM_TSEG choices work. There is periodic TCO timeout occurring. At least with DEBUG_SMI kernel reports low memory corruption. Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-27Revert "sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros"Kyösti Mälkki
This reverts commit 9f0e21a4dae864809e9651403ab5bad48e784bee. It should be allowed for i82801gx/early_init.c to have #include <southbridge/intel/common/pmutil.h> But there is a conflict: src/southbridge/intel/common/pmutil.h: #define TCO1_CNT 0x68 src/southbridge/intel/common/tco.h: #define TCO1_CNT 0x08 Followup works resolve the difficulties around the offset 0x60 used for TCO register bank, tree-wide. Change-Id: I827558a0e0ef1c4d1f866756df51cd1b2abfc7a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-25ACPI MADT: Add LINT1 as NMI sourceKyösti Mälkki
Set of boards and platforms did not have LINT1 configured as NMI source. Change-Id: I65044125562bda363b3a0d92da6137c77a28b587 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69528 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-25ACPI: Use common code for MADT LAPIC NMIsKyösti Mälkki
Use the broadcast ID to deliver LINT1 as NMI to all CPUs, instead of listing individual LAPIC IDs. Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-24sb/intel/i82801gx: Move SPIBASE and SPIBARxx to i82801gx.hElyes Haouas
Also remove unused DEBUG_PERIODIC_SMIS macro. Change-Id: Ieb8487c7757b89a09c1cee4a83f94b9077dac87e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-24sb/intel/i82801gx: Use "sb/intel/common/tco.h" macrosElyes Haouas
Also, use {read,write}_pmbase16() in lpc.c file instead of inw/out. Change-Id: Id281a3478051c4876ccbe26452d8744769c86654 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69878 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-23sb/intel/i82801gx/lpc.c: Use post_code()Elyes Haouas
Use post_code() instead of 'outb(value, CONFIG_POST_IO_PORT)'. Change-Id: I1ba6bff810b61a1249cda6e96eb40f4a81381322 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69901 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-22src/southbridge: Remove unnecessary space after castsElyes Haouas
Change-Id: Ib82968724696110a8d1655928db5b2a665525d20 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69805 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17sb/intel/i82801dx/bootblock.c: Include "i82801dx.h"Elyes Haouas
Change-Id: I58ff31ab98c4310478cf3bbe8aecce4000ac8205 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69717 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-17intel/haswell,lynxpoint: Fix out() parameter orderKyösti Mälkki
Change-Id: Ife134ef6d508113e3cd27b6352ee5044aee43744 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-11-17sb/intel/i82801dx: Improve LPC device early initKyösti Mälkki
Make the implementation more similar to i82801gx, enabling ACPI PM and GPIO register spaces already in bootblock. Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-17sb/intel/common: Fix GPE0 related register conflictKyösti Mälkki
When ACPI GPE0 block was extended to 64 events or 8 bytes, ACPI PM register space was slightly modified. After adjustment, PM2_CNT register moved to 0x50 where register SS_CNT was previously defined to be. For platforms that have a valid use for PM2_CNT==0x50 in their FADT, remove overlapping definition of SS_CNT. On i82801dx/gx ACPI GPE0 supports 32 events, reset_gpe0_status() incorrectly addressed also GPE0_EN register. For a bit cleaner implementation, define GPE0_HAS_64_EVENTS. Change-Id: Iec83e9010146ebd487a61f542ac5c6f4c6a60833 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-17sb/intel/common: Drop duplicate smi_set_eos()Kyösti Mälkki
We have equivalent southbridge_smi_set_eos(). Change-Id: I03a48f0ec9efac2a220aa4ca502a5f504d78c585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-12sb/intel/i82801dx: Clean up includesElyes Haouas
Change-Id: Ib8bfafe9b359856ccfb11a70ab5a6c1ffd453c54 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-11aopen/dxplplusu: Add early GPIO settingsKyösti Mälkki
Required for 2nd COM port to work. Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-10sb/intel/i82870: Use register_new_ioapic()Kyösti Mälkki
Commentary about mixing LAPIC IDs and IOAPIC IDs was wrong, remove it. The only platform affected is aopen/dxplplusu with i82801dx southbridge. Change-Id: I1276a2050cabaaf07f740c2490d92c48bd5801fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10sb,soc/intel: Use register_new_ioapic_gsi0()Kyösti Mälkki
Change-Id: I6b0e4021595fb160ae3bf798468f4505b460266f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10sb,soc/intel: Use acpi_create_madt_ioapic_from_hw()Kyösti Mälkki
Change-Id: I9fd9cf230ce21674d1c24b40f310e5558e65be25 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-09Revert "mb/aopen/dxplplusu: Remove board"Kyösti Mälkki
This reverts commit eb76a455cd39ec59b7f2ba28baeec9538befd59e and applies minor fixes to make it build again. PARALLEL_MP was working prior to board removal and no relevant SMI handlers were implemented. So NO_SMM choice is now selected. Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-07mb/qemu/x86: Remove option for LEGACY_SMP_INITArthur Heymans
This is deprecated after the 4.18 release. Change-Id: I17327c31f8ade51716578e45c2d90a327efcd4ad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69128 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07sb/amd: Remove dropped platformsArthur Heymans
This code is now unused by any platform. Change-Id: I60afbde6ead70f0c887866fc351b4a6a15a89287 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69120 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07mb/aopen/dxplplusu: Remove boardArthur Heymans
This board use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: Idf37ade31ddb55697df1a65062c092a0a485e175 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69114 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-03treewide: Add 'IWYU pragma: export' commentElyes Haouas
This pragma says to IWYU (Include What You Use) that the current file is supposed to provide commented headers. Change-Id: I482c645f6b5f955e532ad94def1b2f74f15ca908 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-10-15treewide: Use 'fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk'Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaecb83c3bc9c75dab427a3ca54da1e6a8f87cf9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-15treewide: Use 'fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk'Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id3002dc976b82f71b1f60a6e32b16d60a7bbbead Reviewed-on: https://review.coreboot.org/c/coreboot/+/68427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-12treewide: Use 'fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ic48c5c165732c8397c06a2362191a94ae5805cf1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7ddb4ea792b9a2153b7c77d2978d9e1c4544535d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'pm2_cnt_len' for 'x_pm2_cnt_blk.bit_width'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I040ddab8845cc2191c6ca5af7f132ec8a504bccf Reviewed-on: https://review.coreboot.org/c/coreboot/+/68274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'gpe0_blk' for 'x_gpe0_blk.addrl'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I05d5097097b925a7bc8058f4c23e7c13a49f03c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'gpe0_blk_len' for 'x_gpe0_blk.bit_width'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I581cacb6086d94fe65e6f4800454f447e1ada07b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->pm_tmr_len' for 'x_pm_tmr_blk.bit_width'Elyes Haouas
Change-Id: Id4e2939b74ec93f50a4bedd0069090f0775b0556 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->pm1_cnt_len' for 'x_pm1a_cnt_blk.bit_width'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I4e468e6bb58adc44bd66149eb79dc885dbf73c67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->pm1_evt_len' for 'x_pm1a_evt_blk.bit_width'Elyes Haouas
Change-Id: I1e51ccad32f1c5e692c76b331eedf4d3bb260d38 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-06treewide: use predicates to check for enabled pci devicesFabio Aiuto
use functions to check for pci devices instead of open-coded solution. TEST: compiled and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: Idb992904112db611119b2d33c8b1dd912b2c8539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68102 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06sb/intel/common/gpio.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Iba746431496b30daba098716337b688314eac283 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06sb/intel/i82801gx/bootblock.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I61d4a188dc9526b71277c05dd317255fc9727414 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06sb/intel/i82801gx/early_init.c: Include common/rcba.hElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I5d9bc4ae942ba171a5d3ef4f77da69398fbac692 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06sb/intel/common/pmbase.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie23472d45c8232f5c907ec1757a648fa1a27d533 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06sb/intel/common/rtc.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ibcd61e44f8e165627851e2c5325985f0765634b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06sb/intel/common/early_smbus.h: Add <device/pci_type.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Icf459f07948cd29eb251b49fcecefb98c5f5f259 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-29treewide: use is_enabled_cpu() on cycles over device listFabio Aiuto
use is_enabled_cpu() on cycles over device list to check whether the current device is enabled cpu. TEST: compile test and qemu run successfully with coreinfo payload Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: If64bd18f006b6f5fecef4f606c1df7d3a4d42883 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67797 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-16bd82x6x/early_pch: enable smbus in bootblock stageHusni Faiz
SMBus is typically enabled in the ROMSTAGE. To get the BOOTBLOCK console message, the SMBus should be enabled in the BOOTBLOCK stage. Change-Id: I97d0afb013ede428383acaa0aa97ab04fe80e2a4 Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67340 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14timer: Change timer util functions to 64-bitRob Barnes
Since mono_time is now 64-bit, the utility functions interfacing with mono_time should also be 64-bit so precision isn't lost. Fixed build errors related to printing the now int64_t result of stopwatch_duration_[m|u]secs in various places. BUG=b:237082996 BRANCH=All TEST=Boot dewatt Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-01amd/*/Makefile.inc: Put common words into common Makefile.incZheng Bao
Definition of FIRMWARE_LOCATION, POUND_SIGN, DEP_FILES, amd_microcode_bins are moved to common Makefile.inc. Change-Id: I5a0ea27002e09d0b879bafad37a5d418ddb4e644 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62658 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-23{sb,soc}/intel: Do not require hda_verb.cAngel Pons
Just use the conditional inclusion through `device/Makefile.inc`. Change-Id: Id363a97460ae2cfe4b10d491d4ef06394eb530c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-11southbridge: Add SPDX identifiers to files missing themMartin Roth
This adds SPDX identifiers to the remaining source files in the southbridge directory that don't already have them. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: If74aa82a7c40293198e07e81ceac52bd8ca8ad27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66500 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-29sb/intel/bd82x6x/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: I4e219bea8df64db1d49beb8534f0f37fee0df5b6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-07-29sb/intel/i82801ix/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: Ifffd21a663739f72a5584e26b79b0627dd532d9e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-07-29sb/intel/i82801jx/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: I3aebd29bba285229979b79867c881018f61e2060 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-07-18sb/amd/cimx/sb800: Remove unused and unsafe macroAngel Pons
The `IMAGE_ALIGN` macro is unsafe because its value is compound and is not enclosed in parentheses, which can cause operation order problems. However, as this macro is unused, remove it instead of fixing it. Change-Id: I099c291f44d5a2c9d32c9ff071374016ed27eee8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-07-18sb/amd/cimx: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Iba81be8ec48fa744f3263e340267a56158656a8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17sb/amd/common: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I04951bf142fc4061960f42ad7ae702a70215e658 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17sb/amd/pi: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I90278683bc22d87364453f316c05afe4cd96b383 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17sb/amd/agesa: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1497c7589570b8ff3873149a0fb212bad96ad432 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17sb/amd/*/*/smbus_spd.c: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I47ee16f2d4be34c42b2e7f9fa4c3a72a7a95967f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17sb/amd/*/*/sata.c: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I4c5dffb32e1ed858e93f95ed17eac894a9100501 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17sb/amd/*/*/smbus.h: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I18120ba93140e2dced7c8d9aafa34a834d1df842 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-14sb/intel/ibexpeak: Perform const correctnessBill XIE
me_bios_path_values[] in me.c should not be mutable. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I56412ff0883e1d37027b989c7ac1bd83e93661f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-14commonlib: Substitude macro "__unused" in compiler.hBill XIE
Since there are many identifiers whose name contain "__unused" in headers of musl libc, introducing a macro which expands "__unused" to the source of a util may have disastrous effect during its compiling under a musl-based platform. However, it is hard to detect musl at build time as musl is notorious for having explicitly been refusing to add a macro like "__MUSL__" to announce its own presence. Using __always_unused and __maybe_unused for everything may be a good idea. This is how it works in the Linux kernel, so that would at least make us match some other standard rather than doing our own thing (especially since the other compiler.h shorthand macros are also inspired by Linux). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-28soc,sb/amd: Change SPI controller resourceKyösti Mälkki
This replaces IORESOURCE_SUBTRACTIVE with IORESOURCE_RESERVE. Change-Id: Ib3d934ca704273daacbeb3c52412bf04e2be7217 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64695 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22intel/broadwell,lynxpoint: Change formula around 4 GiBKyösti Mälkki
Let's not rely on the type to get the correct result, casting 0 to 0ull made the result wrong. Change-Id: I6dfba3800170fdd4267e3bb74c55b05533c101fc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-18sb/intel/i82801ix/smihandler.c: Remove dead incrementElyes Haouas
The value stored to 'data' is never read. So remove dead increment and commented out code. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ifef67fc6415af1260d1a1df54f53fbe67f8860bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-06-07Replace some ENV_ROMSTAGE with ENV_RAMINITKyösti Mälkki
With a combined bootblock+romstage ENV_ROMSTAGE might no longer evaluate true. Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-06cpu/amd/agesa: Use common MRC_CACHE code to save S3 dataArthur Heymans
Use the common code to save data for fast boot or S3 resume. An notable improvement that comes with this, is that the same 4K page is not rewritten all the time. This prolongs the hardware's life. TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine. Change-Id: I0f4f36dcead52a6c550fb5e606772e0a99029872 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44295 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-05-16sb/amd/agesa/hudson/hudson.c: Use BIT() macrosElyes Haouas
Also, code reformatting to reduce coding style difference. Change-Id: I488050a6ab852520734b16032af9a683a3ad1a46 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16sb/amd/*/*/acpi: Reduce stylistic differencesElyes Haouas
Change-Id: I1375b1d18113000b31266030fd7115e23d7cce5f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-19 03:26:53 +0000