diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-12-08 15:29:08 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-12-11 12:43:55 +0000 |
| commit | 56395f4883b8c675dcd82455bb5a6e52c53ab50c (patch) | |
| tree | 7ebd92b913698668e4b4c1f21421778cd4bf705e /src/southbridge | |
| parent | f8fbf0917c722378454b07c2e8ec1a3f87b324ae (diff) | |
sb/intel/common: Move definition of TRAP
Both TRAP and TRP0 are now only defined for i82801gx ASL.
This fixes an issue with updating to IASL 20221020, with many
intel platform builds failing with:
dsdt.asl 38: TRP0 = 0
Error 6084 - ^ Object does not exist (TRP0)
The error was ignored with older IASL.
Change-Id: Ie8a59803f4a27a8315c16bde401f8ca90ee814a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/common/acpi/platform.asl | 10 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/ich7.asl | 8 |
2 files changed, 8 insertions, 10 deletions
diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl index e044f04822..f19ac6c125 100644 --- a/src/southbridge/intel/common/acpi/platform.asl +++ b/src/southbridge/intel/common/acpi/platform.asl @@ -11,16 +11,6 @@ Field (APMP, ByteAcc, NoLock, Preserve) #include <arch/x86/acpi/post.asl> -#if CONFIG(ACPI_SOC_NVS) -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - SMIF = Arg0 // SMI Function - TRP0 = 0 // Generate trap - Return (SMIF) // Return value of SMI handler -} -#endif /* ACPI_SOC_NVS */ - Method(GOS, 0) { /* Determine the Operating System and save the value in OSYS. diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index 6c9c9694f9..f30d3be052 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -15,6 +15,14 @@ Scope(\) TRP0, 8 // IO-Trap at 0x808 } + /* SMI I/O Trap */ + Method(TRAP, 1, Serialized) + { + SMIF = Arg0 // SMI Function + TRP0 = 0 // Generate trap + Return (SMIF) // Return value of SMI handler + } + // ICH7 Power Management Registers, located at PMBASE (0x1f.0 0x40.l) OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) Field(PMIO, ByteAcc, NoLock, Preserve) |