summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
authorElyes Haouas <ehaouas@noos.fr>2022-11-22 15:15:21 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-11-23 15:24:03 +0000
commit334772008c547d971e2591ef53bd570c176572ed (patch)
tree145eb4551a31e5deac20d02f09dfdb7297fe3c7f /src/southbridge
parent9a41333c6bb68a1ebb5cf9d2a0d21257124a735e (diff)
sb/intel/i82801gx/lpc.c: Use post_code()
Use post_code() instead of 'outb(value, CONFIG_POST_IO_PORT)'. Change-Id: I1ba6bff810b61a1249cda6e96eb40f4a81381322 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69901 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index ec0df2722c..d8c977694c 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -445,7 +445,7 @@ static void lpc_final(struct device *dev)
outw(tco1_cnt, DEFAULT_PMBASE + 0x60 + TCO1_CNT);
/* Indicate finalize step with post code */
- outb(POST_OS_BOOT, 0x80);
+ post_code(POST_OS_BOOT);
}
static const char *lpc_acpi_name(const struct device *dev)