diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-10-27 12:25:12 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-03 13:05:17 +0000 |
| commit | 35c3ae3bf4a43a36028fbd9e34ea4cb758029bf1 (patch) | |
| tree | 4b706d4931692f6cde4d16339d7de1b0bf5f1e55 /src/southbridge | |
| parent | 109bd3b796bae2f8333d832e9f0cc778c6663297 (diff) | |
treewide: Add 'IWYU pragma: export' comment
This pragma says to IWYU (Include What You Use) that the current file
is supposed to provide commented headers.
Change-Id: I482c645f6b5f955e532ad94def1b2f74f15ca908
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/i82801ix.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/i82801jx.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/pch.h | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 3 |
6 files changed, 6 insertions, 8 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 15d908ac95..34b36c3866 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -22,7 +22,7 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 -#include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ #if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) #define CROS_GPIO_DEVICE_NAME "CougarPoint" diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index f2ec1c668d..68a32dfa55 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -7,7 +7,7 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 -#include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 56f14b0d2f..f0b60f6215 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -5,7 +5,7 @@ #define DEFAULT_TBAR ((u8 *)0xfed1b000) -#include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ #if CONFIG(BOARD_EMULATION_QEMU_X86_Q35) /* diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 22546897a7..33386f5aad 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -5,7 +5,7 @@ #define DEFAULT_TBAR ((u8 *)0xfed1b000) -#include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ #define DEFAULT_PMBASE 0x00000500 #define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 83e86c266c..1f5b4ea9a9 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -4,6 +4,7 @@ #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H #include <acpi/acpi.h> +#include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ /* PCH types */ #define PCH_TYPE_CPT 0x1c /* CougarPoint */ @@ -24,8 +25,6 @@ #define DEFAULT_PMBASE 0x0500 #define DEFAULT_HECIBAR ((u8 *)0xfed17000) -#include <southbridge/intel/common/rcba.h> - #ifndef __ACPI__ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 7d9fc6d6af..1623274633 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -4,6 +4,7 @@ #define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H #include <acpi/acpi.h> +#include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ #define CROS_GPIO_DEVICE_NAME "LynxPoint" @@ -55,8 +56,6 @@ #define DEFAULT_GPIOSIZE 0x80 #endif -#include <southbridge/intel/common/rcba.h> - #ifndef __ACPI__ #if CONFIG(INTEL_LYNXPOINT_LP) |