diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-12-02 19:16:21 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-12-07 11:33:38 +0000 |
| commit | 521e0460e4292ff0bdaad4ca3861603d13ccfe1d (patch) | |
| tree | d0f50fdf75599471abca42603c6a1f21f348cfb6 /src/southbridge | |
| parent | 2c3ebd8b9d56c01d8e4adadf6f4e4d5b56cdb4e1 (diff) | |
sb,soc/intel,mb: Drop leftover comments and TODOs in ASL
Change-Id: I74f943e9b616458a16aa13c29706cf1551fcbbb2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/pch.asl | 9 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/acpi/ich9.asl | 9 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/acpi/lpc.asl | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/acpi/ich10.asl | 9 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/acpi/lpc.asl | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/pch.asl | 8 |
6 files changed, 0 insertions, 37 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 51c3c48d86..1bfd7201d2 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -5,15 +5,6 @@ Scope(\) { - // IO-Trap at 0x800. This is the ACPI->SMI communication interface. - - OperationRegion(IO_T, SystemIO, 0x800, 0x10) - Field(IO_T, ByteAcc, NoLock, Preserve) - { - Offset(0x8), - TRP0, 8 // IO-Trap at 0x808 - } - // PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l) OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) Field(PMIO, ByteAcc, NoLock, Preserve) diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index 5722b4c741..822bc12958 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -4,15 +4,6 @@ Scope(\) { - // IO-Trap at 0x800. This is the ACPI->SMI communication interface. - - OperationRegion(IO_T, SystemIO, 0x800, 0x10) - Field(IO_T, ByteAcc, NoLock, Preserve) - { - Offset(0x8), - TRP0, 8 // IO-Trap at 0x808 - } - // ICH9 Power Management Registers, located at PMBASE (0x1f.0 0x40.l) OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) Field(PMIO, ByteAcc, NoLock, Preserve) diff --git a/src/southbridge/intel/i82801ix/acpi/lpc.asl b/src/southbridge/intel/i82801ix/acpi/lpc.asl index d2e88902f9..5c68068d4a 100644 --- a/src/southbridge/intel/i82801ix/acpi/lpc.asl +++ b/src/southbridge/intel/i82801ix/acpi/lpc.asl @@ -142,7 +142,6 @@ Device (LPCB) IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH ACPI IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH GPIO }) diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index 2324696d90..d6b84adc05 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -6,15 +6,6 @@ Scope(\) { - // IO-Trap at 0x800. This is the ACPI->SMI communication interface. - - OperationRegion(IO_T, SystemIO, 0x800, 0x10) - Field(IO_T, ByteAcc, NoLock, Preserve) - { - Offset(0x8), - TRP0, 8 // IO-Trap at 0x808 - } - // ICH10 Power Management Registers, located at PMBASE (0x1f.0 0x40.l) OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) Field(PMIO, ByteAcc, NoLock, Preserve) diff --git a/src/southbridge/intel/i82801jx/acpi/lpc.asl b/src/southbridge/intel/i82801jx/acpi/lpc.asl index d2e88902f9..5c68068d4a 100644 --- a/src/southbridge/intel/i82801jx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801jx/acpi/lpc.asl @@ -142,7 +142,6 @@ Device (LPCB) IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH ACPI IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH GPIO }) diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index 50f73cdf9c..8c76002128 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -10,14 +10,6 @@ Scope (\) { - // IO-Trap at 0x800. This is the ACPI->SMI communication interface. - OperationRegion (IO_T, SystemIO, 0x800, 0x10) - Field (IO_T, ByteAcc, NoLock, Preserve) - { - Offset (0x8), - TRP0, 8 // IO-Trap at 0x808 - } - // Root Complex Register Block OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field (RCRB, DWordAcc, Lock, Preserve) |