diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-04-07 07:16:48 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-07 12:53:19 +0000 |
| commit | 11cac784ff788b4f0495758d7f5992e457ea552c (patch) | |
| tree | 15439643f00444d5b3a3d9415475f208faec0ba4 /src/southbridge | |
| parent | 0310d34c2f682b00431a052e770ad44656d1d6f6 (diff) | |
Replace some ENV_ROMSTAGE with ENV_RAMINIT
With a combined bootblock+romstage ENV_ROMSTAGE might no
longer evaluate true.
Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_pch.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/early_init.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/early_init.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/early_init.c | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 6ed3dce8b9..bbbc5e6f7a 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -310,6 +310,6 @@ void early_pch_init(void) setup_pch_gpios(&mainboard_gpio_map); - if (ENV_ROMSTAGE) + if (ENV_RAMINIT) enable_smbus(); } diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 4647bf1c6a..3a0e0b1d77 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -57,7 +57,7 @@ void i82801gx_setup_bars(void) #define TCO_BASE 0x60 -#if ENV_ROMSTAGE +#if ENV_RAMINIT void i82801gx_early_init(void) { enable_smbus(); diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index f781098f33..b8bc9d83c9 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -47,7 +47,7 @@ void i82801ix_early_init(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); - if (ENV_ROMSTAGE) + if (ENV_RAMINIT) enable_smbus(); /* Set up RCBA. */ diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 327c8fc0a5..f7e880cf9e 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -69,7 +69,7 @@ void i82801jx_early_init(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); - if (ENV_ROMSTAGE) + if (ENV_RAMINIT) enable_smbus(); printk(BIOS_DEBUG, "Setting up static southbridge registers..."); |