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authorKyösti Mälkki <kyosti.malkki@gmail.com>2022-11-15 14:00:22 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-11-17 13:34:24 +0000
commitac435b4b911212598ce70092ce5c67a21a9f1111 (patch)
treef944ac62cae2af7666c6b27dce7c708cdf6e28f6 /src/southbridge
parent8d14633dfb21b6789814e1c3ca6700d4be7e50b6 (diff)
intel/haswell,lynxpoint: Fix out() parameter order
Change-Id: Ife134ef6d508113e3cd27b6352ee5044aee43744 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/lynxpoint/pmutil.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c
index 8117b4d3ea..dd7f1990b9 100644
--- a/src/southbridge/intel/lynxpoint/pmutil.c
+++ b/src/southbridge/intel/lynxpoint/pmutil.c
@@ -356,7 +356,7 @@ void enable_tco_sci(void)
u16 gpe0_sts = pch_is_lp() ? LP_GPE0_STS_4 : GPE0_STS;
/* Clear pending events */
- outl(get_pmbase() + gpe0_sts, TCOSCI_STS);
+ outl(TCOSCI_STS, get_pmbase() + gpe0_sts);
/* Enable TCO SCI events */
enable_gpe(TCOSCI_EN);