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2022-01-10soc/amd/common/pi/agesawrapper.c: Include <string.h>Elyes HAOUAS
"memcpy" needs <string.h> Change-Id: I5b7b3a94acbb7e4f9614fcf3f06d68e6ac72f4f1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-07soc/amd/common/block/include/lpc: add comment about RANGE_UNIT valuesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I22f3485ec81f76af7e0e96b7c1271d5ccf52e701 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-07soc/amd/common/lpc/espi_util: move register definitions to header fileFelix Held
Define the register offsets and bits in a separate header file instead of in the middle of the .c file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I814192b2dfeff05877ac857dd89e8cdc7ae5ee25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-07soc/amd/common/block/espi: use lower case hex digits in definitionsFelix Held
coreboot uses lower case hex digits instead of upper case ones. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0955db7afd101ab522845d5911ff971408e520e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60769 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-07soc/amd/common/lpc/espi_util: handle espi_get_configuration errorFelix Held
In espi_wait_channel_ready the return value of espi_get_configuration didn't get checked before. In the case of the espi_send_command call in espi_get_configuration returning CB_ERR, espi_get_configuration didn't write to the local config variable, so if this happens in the first pass of the do-while loop, the following espi_slave_is_channel_ready call would use the uninitialized local config variable as parameter. Fix this by checking the return value of espi_get_configuration. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iff1a0670e17b9d6c6f4daf2ea56badf6c428b8c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-05src/soc/amd: Remove unused <delay.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <delay.h>' -- src/) <(git grep -l 'get_timer_fsb(\|init_timer(\|udelay(\|mdelay(\|delay(' -- src/) |grep "<" Change-Id: Iefb37d28c7f13563fa652cd6b2f661f462a3a32e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-05soc/amd: Remove unused <string.h>Elyes HAOUAS
Change-Id: Ibd3e7a62a2e833017f550eddd915b7dfb539d019 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-01src: Remove duplicated includesElyes HAOUAS
Change-Id: I50cdffca34a6150ac11c3e83e1a603b766d1b84e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-01src: Drop duplicated includesElyes HAOUAS
<types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>, <stdbool.h>, <stdint.h> and <stddef.h> headers. Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-20soc/amd/cezanne: Correct S0i3 verstage softfuse bitRob Barnes
PSP_S0I3_RESUME_VERSTAGE softfuse bit is 58, not 40. BUG=b:202397678 BRANCH=None TEST=Boot guybrush, ensure S0i3 verstage runs with latest PSP. Change-Id: Ia27f6e48e345aac0d5f6579d663a6b655688239a Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-20soc/amd/common/lpc/espi_util: use enum cb_err type for return valuesFelix Held
Use enum cb_err as return type of all remaining functions that only return success or failure. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6cff8480d99641fdfb613bb3e4edc4055ad5efc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd/common/lpc/espi_util: use enum cb_err type for return valuesFelix Held
Use enum cb_err as return type of all functions that aren't exposed outside of this compilation unit. The checks if a function has returned a failure are replaced with checks if the return value isn't CB_SUCCESS which is equivalent if only those two values are used, but also detects a failure if any unexpected value would be returned. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If8c703f62babac31948d0878e91bd31b31bebc01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd/common/lpc/espi_util: simplify espi_configure_decodesFelix Held
The intermediate ret variable isn't needed. espi_open_generic_io_window only returns 0 or -1, so if ret is != 0, it has to be -1. This is a preparation to use the enum cb_err type for the return values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6c7f4cedf8c2defadcf4c4da1697a97c7b401f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd/common/lpc/espi_util: simplify espi_get_general_configurationFelix Held
The intermediate ret variable isn't needed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e6747cf468c5ba8da6c1a3b20022851e32ad951 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd/cezanne/fch: disable 48MHz output in S0i3Felix Held
S0i3 is a low power state which reduces the power consumption to about the level of the S3 suspend state where the DRAM is kept in a self- refresh state and most of the rest of the system is powered down. So everything that can be switched off in the S0i3 state should be switched off in order to maximize the standby time. BUG=b:210722314 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If445f5825dc7b795c95d73c061156cc485421ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/60125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-20soc/amd/stoneyridge/fch: add GNVS-related TODOsFelix Held
The AOAC device states shouldn't be stored in GNVS, but be read from the AOAC registers during runtime. Same for the EHCI controller's BAR0. The location and size of the XHCI firmware can either be statically determined at build-time or have coreboot generate ACPI objects that contain the needed addresses. Since I can't easily test changes that require booting to a desktop on Stoneyridge at the moment, only add TODOs for now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I3691b05606b9430cb60923780a6131993a9887d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd/stoneyridge: split southbridge codeFelix Held
Split the southbridge code into a bootblock and a ramstage part to align it more with Picasso and Cezanne. Also move the implementation of fch_clk_output_48Mhz to the end of early_fch.c since it's not really related to the functions that were previously around it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib660fbef8dc25ba0fab803ccd82b3408878d1588 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd/stoneyridge: factor out AGESA-wrapper related FCH functionsFelix Held
Split the code that gets called from the AGESA wrapper from the rest of the FCH/southbridge code that directly interacts with the hardware. Since the remaining parts of southbridge.c aren't used in romstage, drop it from the list of build targets for romstage. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6197add0e1396a82545735653110e1e17bf9c303 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd/stoneyridge: factor out early AOAC initializationFelix Held
Factor out enable_aoac_devices out of southbridge.c to aoac.c to align Stoneyridge more with Picasso and Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ied4d821138507639cad1794f6c5017b5873b761f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd: remove root of SoC directory from include pathFelix Held
We shouldn't be providing -I include paths to the root of the soc specific directory. It allows for lazy includes that can collide, but there's no way of knowing the winning path since the winning path is determined by Makefile.inc parsing order. This is taken from CB:41355 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I45ed219e4e0cccf3d4f04cc70dc1ef77c518afff Reviewed-on: https://review.coreboot.org/c/coreboot/+/60201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-20soc/amd/stoneyridge/include/southbridge: remove unneeded chip.h includeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b37efc89e505c2de99536b59e7d7e2bb1d54bff Reviewed-on: https://review.coreboot.org/c/coreboot/+/60199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-18soc/amd/cezanne/acpi: Add support for RTC workaroundRaul E Rangel
The RTC on Cezanne is an unstable wake source when the system is in S0i3. We instead need to use an internal timer that triggers a GPIO that acts as a wake source. This change provides the ACPI necessary to allow the OS to manage the wake source. BUG=b:209705576 TEST=Boot guybrush with this patch and several OS patches. Verified the OS sets the correct wake bit, the system correctly suspends and resumes, and the wake source is correctly accounted for. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1f14d14df5d30d48d244416f2ec8c10ac5c8040e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Limonciello <mario.limonciello@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-18soc/amd/common/block/acpimmio/print_reset_status: add missing status bitFelix Held
Both the Picasso PPR #55570 Rev 3.18 and the Cezanne PPR #56569 Rev 3.03 define bit 9 of the PM_RST_STATUS register as internal Thermal Trip reset status bit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ida8b13fe62b16c18fc9924520b83220e73eca624 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-15soc/amd/common/block/psp: move psp_notify_dram to psp_gen1.cFelix Held
The MBOX_BIOS_CMD_DRAM_INFO PSP mailbox command is only available on the first generation of PSP mailbox interface and not on the second generation. The second generation of the PSP mailbox interface was introduced with the AMD family 17h SoCs on which the DRAM is already initialized before the x86 cores are released from reset. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97b29fdc4a71d6493ec63fa60f580778f026ec0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-15soc/amd/common/block/spi/fch_spi_ctrl: improve printk messagesFelix Held
Replace FCH_SC with FCH SPI in the printk messages to make those a bit clearer and also remove an unneeded line break in another printk call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6ff02163e6a48a2cc8b7fe89b15826e154715d29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15soc/amd/common/block/spi/fch_spi_ctrl: handle failure in execute_commandFelix Held
When wait_for_ready returned a timeout, execute_command still ended up returning success. Fix this be returning a failure in this case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id012e74e26065c12d003793322dcdd448df758b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15soc/amd/common/block/spi/fch_spi_ctrl: rework dump_stateFelix Held
Introduce and use enum spi_dump_state_phase to indicate from which phase of the SPI transfer dump_state gets called to print the relevant debug information for that phase. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2f54d4a7eb2f3b9756b77a01533f7c99e8597bfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/60118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15soc/amd/common/include/spi: add Cezanne-specific commentFelix Held
The Cezanne PPR #56569 Rev 3.03 has one more SPI FIFO bytes defined compared to the previous generations. It is unclear if adding some special handling for Cezanne would be worth the effort, since the current code just doesn't use the last byte which should be safe to do, since this only affects the maximum number of bytes that can be used for one SPI transaction. Having another byte to use on Cezanne wouldn't reduce the number of SPI transactions to write a 256 byte data block. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic730f4fe838f59066120c811833995c132c84c1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/60117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15soc/amd/common/include/spi: fix SPI_FIFO_LAST_BYTE defineFelix Held
The last byte of the SPI FIFO SPI_FIFO_LAST_BYTE is at offset 0xc6 of the SPI controller's MMIO region for Stoneyridge and Picasso. Both SPI_FIFO_LAST_BYTE and SPI_FIFO_DEPTH had an off-by-one error that ended up cancelling out each other, so the resulting value for SPI_FIFO_DEPTH isn't changed. TEST=Timeless build results in identical image for Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1676be902ccf57e2e9f69d81251b4315866a0628 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-14soc/amd/{cezanne,common}: Add PSP_S0I3_RESUME_VERSTAGE Kconfig optionRob Barnes
Add PSP_S0I3_RESUME_VERSTAGE Kconfig option. When enabled, verstage will be run in PSP during S0i3 resume. Setting softfuse bit 40 enables this in PSP. BUG=b:200578885, b:202397678 BRANCH=None TEST=Verstage runs during s0i3 resume on Nipperkin Change-Id: I2c185f787c1e77bd09f6cbbb1f47deb665ed0c79 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-13soc/amd/cezanne: Don't select CPU_INFO_V2 explicitlyNico Huber
It's already implied by PARALLEL_MP now. Change-Id: Ia76f1a925b2c0ebbba0bf20b094e716708d540c2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-09soc/amd/stoneyridge: use common fch_spi_early_initFelix Held
All SPI interface setup related functionality that Stoneyridge implemented in its southbridge code is already present in the common AMD SoC code, so use that code instead. The common fch_spi_early_init function requires the SPI controller's base address to be set, so call lpc_set_spibase(SPI_BASE_ADDRESS) right before it. fch_spi_early_init then calls lpc_enable_spi_rom and lpc_enable_spi_prefetch which can be removed from the board code now. Next it calls fch_spi_configure_4dw_burst which does the same as the now removed sb_disable_4dw_burst function when SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST is set to n which is the default. This option can also only be set to y for SoCs that aren't Stoneyridge. Finally fch_spi_early_init calls fch_spi_config_modes which configures the SPI mode and speed settings according to the Kconfig settings and the settings in the amdfw part. On Kahlee this was done by calls to sb_read_mode and sb_set_spi100 before. The previous patch added the remaining Kconfig settings, so the resulting register values don't change in the non-EM100 case. In the EM100 case the TPM speed is changed from 64 to 16 MHz. TEST=Both the non-EM100 mode with a real SPI flash and the EM100 mode with a first-generation EM100 results in Google/Barla reaching the payload and the show_spi_speeds_and_modes call in bootblock prints the expected settings: relevant bootblock console output in non-EM100 case: SPI normal read speed: 33.33 MHz SPI fast read speed: 66.66 Mhz SPI alt read speed: 66.66 Mhz SPI TPM read speed: 66.66 Mhz SPI100: Enabled SPI Read Mode: Dual IO (1-2-2) relevant bootblock console output in EM100 case: SPI normal read speed: 16.66 MHz SPI fast read speed: 16.66 MHz SPI alt read speed: 16.66 MHz SPI TPM read speed: 16.66 MHz SPI100: Enabled SPI Read Mode: Normal Read (up to 33M) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f37a3b040808d6a5a8e07d39b6d4a1e1981355c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-09soc/amd/common/block/psp: add psp_efs.c to build for both PSP GEN1&2Felix Held
The PSP EFS code to get the SPI mode and speed from the amdfw part of the firmware image also works for Stoneyridge which is the one SoC that selects SOC_AMD_COMMON_BLOCK_PSP_GEN1. Also amdblocks/psp_efs.h already handles the SOC_AMD_STONEYRIDGE case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibddd3f9237e561d9f0f6b4ad70f59cce1f956986 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-08soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resumeRaul E Rangel
According to https://uefi.org/specs/ACPI/6.4/04_ACPI_Hardware_Specification/ACPI_Hardware_Specification.html#pm1-event-grouping > For ACPI/legacy systems, when transitioning from the legacy to the G0 > working state this register is cleared by platform firmware prior to > setting the SCI_EN bit (and thus passing control to OSPM). For ACPI > only platforms (where SCI_EN is always set), when transitioning from > either the mechanical off (G3) or soft-off state to the G0 working > state this register is cleared prior to entering the G0 working state. This means we don't want to clear the PM1 register on resume. By clearing it the linux kernel can't correctly increment the wake count when the power button is pressed. The AMD platforms implement the _SWS ACPI methods, but the linux kernel doesn't actually use these methods. BUG=b:172021431 TEST=suspend zork and push power button and verify power button wake_count increments. Verified other wake sources still work. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-08soc/amd/stoneyridge/southbridge: drop ENV_X86 checkFelix Held
Stoneyridge selects ARCH_X86 unconditionally and all coreboot code will run on the x86 cores. On Picasso and later, the Chromebooks run verstage on the PSP which is an ARM V7 core which needs some special handling cases in the code, but this doesn't apply to Stoneyridge. TEST=Timeless build results in an identical image for Google/Careena. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I013efd13b56c0191af034a8c4b58e9b26a31c6e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-08soc/amd/{cezanne,picasso,stoney}: Clear PM/GPE when enabling ACPIRaul E Rangel
According to https://uefi.org/specs/ACPI/6.4/16_Waking_and_Sleeping/sleeping-states.html?highlight=power%20states# > For ACPI/legacy systems, when transitioning from the legacy to the G0 > working state this register is cleared by platform firmware prior to > setting the SCI_EN bit. This change makes sure we clear the PM/GPE blocks are cleared before enabling the SCI_EN bit. BUG=b:172021431 TEST=Boot guybrush and morphius to OS and verify suspend resume still works. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icc6f542185dc520f8d181423961b74481c0b5506 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-08soc/amd/stoneyridge/southbridge: fix setting SPI_USE_SPI100Felix Held
Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities of the SPI interface. The reference code for Stoneyrige also only sets the SPI_USE_SPI100 bit and doesn't zero out the other bits. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4d32fc2084bb34ea57924bae68511c6836587790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-08soc/amd/common/block/spi: fix setting SPI_USE_SPI100 in SPI100_ENABLEFelix Held
Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities of the SPI interface. The reference code for both Picasso and Cezanne also only sets the SPI_USE_SPI100 bit and doesn't zero out the other bits. TEST=Verified that Mandolin still boots. It didn't show any signs of possibly related instabilities before though, so this test doesn't say much. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71c2ec1729d5cb4cdff6444b637af29caaa6f1c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-08soc/amd/common/block/include/spi: update fch_spi_early_init descriptionFelix Held
commit 90ac882a32075b44435aa19ea664b89b79cac76e (soc/amd/common/block/ spi: introduce SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST) introduced a Kconfig option to enable/disable the 4DW burst support in the SPI flash data prefetcher, but missed to update the documentation above the fch_spi_early_init prototype, so update the outdated documentation now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I07c4b0b02251da63d34a172e2636894e99845d6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-08mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_initRaul E Rangel
These functions can't be weak, because they actually need to configure the GPIOs for eSPI and the TPM. With this change zork boots again. I also noticed that zork doesn't use the early table in bootblock. This means that zork will only boot if psp_verstage is enabled. BUG=b:209465425 TEST=boot zork to ramstage Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I384fd578efe7da0a3d74829cccf38c3ed524f130 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-08soc/amd: use KiB and MiB definitionsFelix Held
Use KiB and MiB instead of multiplying/dividing with/by the numeric value when doing region size calculations. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I56c380190b11aa3214cce31b82974327e3d15000 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-03soc/amd/cezanne: Enable secure countersKarthikeyan Ramasubramanian
Guybrush uses secure counters to protect against High Definition (HD) protected content rollback. These secure counters are hosted in TPM NVRAM. Enable secure counters so that they are defined in PSP verstage. BUG=b:205261728 TEST=Build and boot to OS in Guybrush. Ensure that the secure counters are defined successfully in TPM NVRAM. Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-30soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1Felix Held
Despite Stoneyridge being one only SoC in soc/amd that uses the first generation of the PSP mailblox interface, this code is common for all SoCs that use the first PSP mailbox interface generation, so move it to the common PSP generation 1 code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59701 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-30soc/amd/cezanne: add missing PM_ACPI_* bit definitionsFelix Held
This part was copied from Picasso but Cezanne has some more bits used so add the definitions now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icd128dca1ec30e7c70501c0e64482159be71cc7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-30soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defsFelix Held
Both SPI_ROM_BIOS_SEMAPHORE and SPI_ROM_EC_SEMAPHORE bits in the LPC_PCI_CONTROL are defined in the Stoneyridge BKDG #55072 Rev 3.04, Raven1 and Picasso PPR #55570 Rev 3.18, Raven2 PPR #55772 Rev 3.08 and Cezanne PPR #56569 Rev 3.03 which are all platforms that use this code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I855e640d020daf21c9f5b2f62a2ad0fd0274a575 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-29soc/amd/common/block/lpc: use 32 bit accesses in lpc_enable_port80Felix Held
When using 32 bit PCI accesses in lpc_enable_port80, we can use the LPC_IO_OR_MEM_DECODE_ENABLE and DECODE_IO_PORT_ENABLE4 defines and don't need to re-define bits with offsets from the beginning of the third byte within this 32 bit register. This allows to drop the LPC_IO_OR_MEM_DEC_EN_HIGH register definition which points to LPC_IO_OR_MEM_DECODE_ENABLE + 2 and to drop the re-definitions of the bit re-definitions with a different offset. The code in lpc_enable_port80 was originally copied from sb/amd/agesa/ hudson/early_setup.c which might be sort-of a copy from what the AGESA reference code does. TEST=When commenting out SOC_AMD_COMMON_BLOCK_USE_ESPI in the Kconfig of Mandolin and selecting AMD_LPC_DEBUG_CARD, all POST codes still get shown on the POST code LED display when this patch is applied. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I001bb1c2ccf99e36d4fbd73d3bf96b78ddb87d67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-29soc/amd/common/block/lpc/lpc_util: drop lpc_enable_pci_port80Felix Held
This function is unused and none of the SoCs using this code has a physical PCI interface any more, so drop this function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia5c5a8ec29264a075fefe75038ef2a84684d6427 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-29src/cpu,soc/amd/common/block/cpu: Add preload_microcodeRaul E Rangel
This will enable preloading the microcode. By preloading the file, into cbfs_cache we reduce boot time. BUG=b:179699789 TEST=Boot guybrush with CL chain and see microcode preloading and a reduction of 1 ms. | 112 - started reading uCode | 1.041 | 1.204 Δ( 0.16, 0.01%) | | 113 - finished reading uCode | 1.365 | 0.011 Δ( -1.35, -0.10%) | Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If0c634c692c97769e71acd1175fc464dc592c356 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-29soc/amd/stoneyridge/psp: use PSP_MAILBOX_BAR defineFelix Held
PSP_MAILBOX_BAR is defined as PCI_BASE_ADDRESS_4, so use it instead of PCI_BASE_ADDRESS_4 in the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8658b674b9adea85dfc71d7036ccf3ae17464b58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-29soc/amd/common/block/psp/psp_def: drop PSPV2_STATUS_* definesFelix Held
PSPV2_STATUS_ERROR and PSPV2_STATUS_RECOVERY aren't used and the bit definitions are also wrong, so drop those defines. For the PSP mailbox interface version 2, struct pspv2_mbox is used to access the correct status bits. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8e2aadfde00e2f7b0f99b462b8e3d6954959a584 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-29cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_NEED_1_SIPISubrata Banik
This patch renames X86_AMD_INIT_SIPI Kconfig to leverage the same logic (to skip 2nd SIPI and reduce delay between INIT and SIPI while perform AP initialization) even on newer Intel platform. Change-Id: I7a4e6a8b1edc6e8ba43597259bd8b2de697e4e62 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56651 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-25soc/amd/*/data_fabric: use DF_ prefix for bit and shift definesFelix Held
Adding the DP_ prefix to the defines for MMIO_NP, MMIO_WE and MMIO_RE clarifies the scope of those definitions. For consistency also add this prefix to MMIO_DST_FABRIC_ID_SHIFT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a509ccc071aa51a67552fb9e7195358a76fe4dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/*/include/data_fabric: make MMIO_NP definition SoC-specificFelix Held
On Picasso the MMIO_NP bit in the D18F0_MMIO_CTRL0 data fabric register is bit 12, but that has changed to bit 16 in Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I64c06b84e2c0737b259077e7932f418306638e19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/aoac: fix typo in FCH_AOAC_REF_CLK_OK_STATE definitionFelix Held
The bit is called REF_CLK_OK_STATE and not RST_CLK_OK_STATE, so change the name of the define to FCH_AOAC_REF_CLK_OK_STATE. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iae26db94d83ebb2cb799f6d3e0bec37c8e849219 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: add missing de-glitching definesFelix Held
There were only definitions for removing low, high or both glitches, but not to not remove glitches, so add this too for completeness. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I650f7754546935539339c02bb6a94bb3f855d4ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/59631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: rework de-glitching definesFelix Held
I found the name of the DEB_GLITCH_NONE definition a bit misleading, so change it to DEB_GLITCH_REMOVE which should clarify what this will do. The description for this value in the PPR/BKDG is "Remove glitch". This also puts the define in line with GPIO_DEB_REMOVE_GLITCH which is the only place where DEB_GLITCH_NONE/DEB_GLITCH_REMOVE is used. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I59648710e0ff28c2026e1b2cc7e433cafb2f2807 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: use tabs for indentationFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibf7482d20c6d27b2314ec8a31c349eb90c8a8feb Reviewed-on: https://review.coreboot.org/c/coreboot/+/59629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/gpio: drop unused gpio_get_addressFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5b47324af368f81288e9e9be65fe0f1ae2fa3697 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/acpi/gpio_bank_lib: drop unused methodsFelix Held
Those methods were only in the non-common Stoneyridge GPIO ACPI code that got dropped, so drop those unused methods too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I519d88ffa1d5d4823cce4876ecf59b9019f676e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: drop unused GPIO_PIN_IN/OUTFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idf00879701b223ecaca74aef2a51a1b86d2c6ce3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_ACPI_GPIOFelix Held
Stoneyridge uses the same GPIO bank peripheral as Picasso and Cezanne so we can use the common AMD SoC GPIO ACPI code. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa1fc923cd5b779765917b171b5a7222f18a176a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: de-duplicate pin status bit defsFelix Held
De-duplicate the definitions for the pin status bit and use this new definition in both the C and the ACPI code. TEST=Timeless build results in identical image for amd/mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8b0fe7dbec5dac176cdfa9690862433f202fb552 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: drop duplicate wake bit defsFelix Held
The GPIO_WAKE_* definitions are the ones that are used in the code, so drop the unused GPIO_*_WAKE_EN definitions for the same bits. Also move the GPIO_WAKE_* definitions to the place the GPIO_*_WAKE_EN ones were before this patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I622673cc72107908b525a65212061062f32e13dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: use bit definitions for masksFelix Held
All bits covered by the bit masks GPIO_INT_ENABLE_MASK, GPIO_PULL_MASK, GPIO_STATUS_MASK and GPIO_WAKE_MASK already have definitions in the code so use those instead of magic numbers. TEST=Timeless build results in identical image for amd/mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0bc9e1cecf2f063b42de3f8875fee421dd256648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: remove unneeded line breakFelix Held
The definitions of GPIO_INT_ENABLE_STATUS_DELIVERY and GPIO_TIMEBASE_62440uS fit into 96 characters, so remove the unneeded line breaks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b9c3885259b9acf0539eed14e23fbbb0deccea7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: drop 8k pullup defineFelix Held
The corresponding bit is marked as reserved in the following versions of the documentation for all SoCs using this code: Mullins: BKDG #52740 Rev 3.05 Stoneyridge: BKDG #55072 Rev 3.04 Raven1, Picasso: PPR #55570 Rev 3.16 & 3.18 Raven2: PPR #55772 Rev 3.08 Cezanne: PPR #56569 Rev 3.03 The old Rev 3.14 of the Picasso PPR #55570 had the bit 19 defined as PullUpSel, but this is no longer the case in newer versions. It is unclear if this got de-featured or if it was never present in the silicon. To be consistent with the current documentation, drop this define. This patch also change the definition of GPIO_PULL_MASK to only cover the bits used for the feature. The Cezanne PPR #56569 Rev 3.03 states a default value of 0 for this bit after reset, so the resulting values in the register aren't expected change. The other PPRs/BKDGs don't specify a reset value for this bit, but it's likely safe to assume that all SoCs that use the new GPIO interface use the same GPIO building block. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaf2d4eec7a13e558c75d7edea343b876909a5b33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-24soc/amd/common/block/include/acpi: fix reference to main acpi includeFelix Held
commit e0844636aca974449c7257e846ec816db683d0b9 (acpi: Move ACPI table support out of arch/x86 (2/5)) moved the main acpi header file from arch/x86/include/acpi/acpi.h to include/acpi/acpi.h, so change the comment in here to point to the current location. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5fddd1cd5eefd83816b1c966b5c7edf53eb2486d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-24soc/amd/common/block/include/gpio_defs: add GPIO IRQ status registersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I585691038690f1d6855ab09f1ca5791a18cfdbfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/59590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-24soc/amd/common/block/include/gpio_defs: use lower case in hex numbersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icb1c7b243f655225347ba2a78c80e6e8653e8cda Reviewed-on: https://review.coreboot.org/c/coreboot/+/59589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-24soc/amd/picasso,stoneyridge/acpi: use define for RTC_DATE_ALARMFelix Held
Cezanne already uses a define for this and it's better to define and use constants instead of magic values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa4b3b3cdb161670128b284a3396fc5a85545608 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-22soc/amd/psp_verstage: Init TPM on S0i3 resumeRob Barnes
Add option to initialize the TPM in PSP verstage during s0i3 resume. This is needed if the TPM is reset in s0i3. FSDL is handling restoring everything else, so only the minimum TPM initialization is done. Move aoac and i2c init before psp_verstrage_s0i3_resume becasue i2c needs to be ready before attempting to restore tpm. BUG=b:200578885,b:197965075 TEST=Multiple cycles of S0i3 suspend resume. ~66ms of additional delay. BRANCH=None Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-18mb/google/guybrush: Add variant_tpm_gpio_tableRob Barnes
Add separate gpio table for TPM i2c and interrupt. Remove TPM gpios from early_gpio_table. This allows for initializing TPM gpios separately from other gpios. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59083 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-18amdfwtool: Call the set_efs_table for StoneyridgeZheng Bao
Related to https://review.coreboot.org/c/coreboot/+/58555 commit-id: 35b7e0a2d82ac In 58555, we added the SOC ID for Stoneyridge in amdfwtool command line. But it raised building error because it then called "set_efs_table" without setting SPI mode. So we skipped calling that. But in set_efs_table, it has case for Stoneyridge. The boards also need to have this setting. So we remove the skipping and give the proper SPI mode in mainboard Kconfig. Change-Id: I24499ff6daf7878b12b6044496f53379116c598f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-17soc/amd/psp_verstage: Split up verstage_soc_initRob Barnes
Make psp verstage initialization more granular be splitting verstage_soc_init into separate functions. Specifically, create soc init functions for espi, i2c spi, and aoac. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I489889a0dfd4016aa4f2b53a2c6a7a1ea4459e60 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-11-16lib/prog_loaders, soc/amd/: Make payload_preload use cbfs_preloadRaul E Rangel
Now that CBFS has this functionality built in, we no longer need to manually code it. payload_preload used to use the payload_preload_cache region to store the raw payload contents. This region was placed outside the firmware reserved region, so it was available for use by the OS. This was possible because the payload isn't loaded again on S3 resume. cbfs_preload only uses the cbfs_cache region. This region must be reserved because it gets used on the S3 resume path. Unfortunately this means that cbfs_cache must be increased to hold the payload. Cezanne is the only platform currently using payload_preload, and the size of cbfs_cache has already been adjusted. In the future we could look into adding an option to cbfs_preload that would allow it to use a different memory pool for the cache allocation. BUG=b:179699789 TEST=Boot guybrush and verify preloading the payload was successful CBFS DEBUG: get_preload_rdev(name='fallback/payload') preload successful Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idc521b238620ff52b8ba481cd3c10e5c4f1394bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-15soc/amd/common/block: Add spi_hw mutexRaul E Rangel
There are currently two users of the SPI hardware, the LPC SPI DMA controller, and the boot_device_rw device. We need to ensure exclusivity to the SPI hardware otherwise the SPI DMA controller can be interrupted and it will silently skip transferring some blocks. Depending on the SPI speed, this change might add a small delay when clearing the elog since a DMA transaction might be in flight. I'll continue optimizing the boot flow to avoid the delay. BUG=b:179699789 TEST=Hack up the code to interleave SPI transactions and verify this patch fixes the silent data corruption. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5eee812a6979c8c0fb313dd2fbccc14b73d7d741 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-15amdfwtool: Set soc name for StoneyridgeZheng Bao
For the stoneyridge, soc_name is not set in Makefile, so set_efs_table is not called. Keep it unchanged. Change-Id: I0e82188ce64733420a578446e22a077ef789be92 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15soc/amd/stoneyridge/include/pci_devs: remove unused DEVID definesFelix Held
None of the *_DEVID defines was used in the code, so drop those. The SoC code uses the PCI ID defines from include/device/pci_ids.h instead. Since it might still be useful to have the PCI device IDs as a reference in the SoC's pci_devs.h, add those as comments instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7c77d648dac57b15b56f631bd8b2494676c00a8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-13Add ENV_STAGE_SUPPORTS_SMP to clean up spinlock stubsKyösti Mälkki
CONFIG(SMP) was an invalid condition to use in cases where one stage requires spinlocks and another one does not. The stage not requiring spinlock still required <smp/spinlock.h> to be implemented with no-op stubs. This reverts commit 037ee4b556 soc/amd/picasso: Add dummy spinlock for psp_verstage Change-Id: Iba52febdeee78294f916775ee9ce8a82d6203570 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-13mb/google/guybrush: Add variant_espi_gpio_tableRob Barnes
Add separate gpio table for early eSPI bus init. Remove espi GPIO from early_gpio_table. This allows for initializing eSPI separately from other GPIOs. Simplify verstage_mainboard_early_init. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-11-13sod/amd/cezanne: Use LZ4 for FSP-M when using SPI DMARaul E Rangel
This change adds about 30 KiB to FSP-M. When not using the SPI DMA controller, this change actually has a ~7 ms boot time penalty. When we use the DMA engine, we end up with about a 5 ms decrease. Once we switch to 100 MHz SPI this will help even more since we have effectively eliminated the decompression time. BUG=b:179699789 TEST=Boot nipperkin to OS and take boot time measurements fspm.bin 0x2efc0 fsp 90953 LZMA (233472 decompressed) fspm.bin 0x2cfc0 fsp 121156 LZ4 (233472 decompressed) - FSP-M / no async - | 508 - finished loading body | 177.019 | 179.384 Δ( 2.36, 0.16%) | ... | 970 - loading FSP-M | 0.346 | 0.346 Δ( 0.00, 0.00%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.009 | 0.01 Δ( 0.00, 0.00%) | | 18 - finished LZ4 decompress (ignore for x86) | 53.916 | 59.475 Δ( 5.56, 0.37%) | - FSP-M / async - | 508 - finished loading body | 177.185 | 179.689 Δ( 2.50, 0.18%) | ... | 970 - loading FSP-M | 0.989 | 0.99 Δ( 0.00, 0.00%) | | 17 - starting LZ4 decompress (ignore for x86) | 9.483 | 12.877 Δ( 3.39, 0.24%) | | 18 - finished LZ4 decompress (ignore for x86) | 10.833 | 0.312 Δ(-10.52, -0.75%) | Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7d0363d27d98d4ed3afc6f802a13ff7986391921 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-13soc/amd/psp_verstage: Reboot on verstage_soc_early_init failRob Barnes
Calling reboot_into_recovery with NULL context fails. Initializing ctx early also fails because the cmos is not ready until after verstage_soc_early_init. So just reboot and hope for the best. BUG=None TEST=Boot guybrush, suspend/resume guybrush BRANCH=None Change-Id: I7267a14ab048781b8998d3a6f4220de10e7df250 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-12soc/amd/cezanne: Use LZ4 for FSP-SRaul E Rangel
This change increases the fsps.bin by 20 KiB, but it decreases decompression time. When not using preloading we save about 4 ms, when using preloading we save about 6. BUG=b:179699789 TEST=Boot nipperkin to OS fsps.bin 0x4afc0 fsp 66253 LZMA (200704 decompressed) fsps.bin 0x45fc0 fsp 87157 LZ4 (200704 decompressed) - FSP-S / no async - | 505 - starting to verify keyblock/preamble (RSA) | 9.36 | 11.012 Δ( 1.65, 0.11%) | ... | 971 - loading FSP-S | 7.095 | 6.141 Δ( -0.95, -0.07%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.009 | 0.008 Δ( -0.00, -0.00%) | | 18 - finished LZ4 decompress (ignore for x86) | 15.149 | 8.98 Δ( -6.17, -0.42%) | | 954 - calling FspSiliconInit | 0.038 | 0.037 Δ( -0.00, -0.00%) | - FSP-S / async - | 508 - finished loading body | 177.978 | 179.689 Δ( 1.71, 0.12%) | ... | 971 - loading FSP-S | 6.928 | 7.225 Δ( 0.30, 0.02%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.011 | 0.01 Δ( -0.00, -0.00%) | | 18 - finished LZ4 decompress (ignore for x86) | 8.312 | 0.241 Δ( -8.07, -0.58%) | | 954 - calling FspSiliconInit | 0.091 | 0.09 Δ( -0.00, -0.00%) | Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib0479ed3c92158799ea2b023bd2ce4c5c09757dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-12soc/amd/cezanne: Preload FSP-SRaul E Rangel
FSP-S is normally memmapped and then decompressed. There are about 7 ms between starting ramstage, and loading FSP-S. By preloading we can ensure the fsps.bin is already in RAM by the time we need it. This reduces boot time by about 7 ms. BUG=b: TEST=Boot nipperkin and see ~7ms reduction in boot time | 10 - start of ramstage | 0.044 | 0.044 Δ( 0.00, 0.00%) | | 30 - device enumeration | 1.899 | 2.073 Δ( 0.17, 0.01%) | | 971 - loading FSP-S | 6.645 | 6.628 Δ( -0.02, -0.00%) | | 15 - starting LZMA decompress (ignore for x86) | 0.016 | 0.01 Δ( -0.01, -0.00%) | | 16 - finished LZMA decompress (ignore for x86) | 15.266 | 8.316 Δ( -6.95, -0.47%) | | 954 - calling FspSiliconInit | 0.08 | 0.09 Δ( 0.01, 0.00%) | CBFS DEBUG: _cbfs_alloc(name='fsps.bin', alloc=0xc9761e5c(0xc97a3f0c), force_ro=false, type=-1) CBFS: Found 'fsps.bin' @0x1a1fc0 size 0x102cd in mcache @0xc97dd208 waiting for thread took 1 us <-- fsps.bin was preloaded CBFS DEBUG: get_preload_rdev(name='fsps.bin') preload successful Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5a728047b8ad92d70bba8485017579aa3df48d95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-12soc/amd/common/block/lpc: Set FSP-S/M alignment to 64 when using SPI DMARaul E Rangel
This will enable reading FSP-S/M using the SPI DMA controller. BUG=B:179699789 TEST=Build guybrush with SPI DMA enabled and verify alignment is set Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I282b9989d8e95c93603c6f69616a8f236a4e2e35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-11arch/x86: Refactor the SMBIOS type 17 write functionSubrata Banik
List of changes: 1. Create Module Type macros as per Memory Type (i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation issue due to renaming of existing macros due to scoping the Memory Type. 2. Use dedicated Memory Type and Module type for `Form Factor` and `TypeDetail` conversion using `get_spd_info()` function. 3. Create a new API (convert_form_factor_to_module_type()) for `Form Factor` to 'Module type' conversion as per `Memory Type`. 4. Add new argument as `Memory Type` to smbios_form_factor_to_spd_mod_type() so that it can internally call convert_form_factor_to_module_type() for `Module Type` conversion. 5. Update `test_smbios_form_factor_to_spd_mod_type()` to accommodate different memory types. 6. Skip fixed module type to form factor conversion using DDR2 SPD4 specification (inside dimm_info_fill()). Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx. BUG=b:194659789 TEST=Refer to dmidecode -t 17 output as below: Without this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Unknown .... With this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Row Of Chips .... Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-10soc/amd/cezanne/fsp_m_parameters: add curly braces around else blockFelix Held
Since the if block contains multiple statements, it uses curly braces around them, so also add curly braces around the else block even though it only contains one statement. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia8d6b45ec16916ff77078446414de259cffa1475 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59070 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-10soc/amd/cezanne,picasso/include/southbridge: use bitwise or in definesFelix Held
Use bitwise or instead of additions to build bit masks with multiple bits set. TEST=Timeless build results in identical image on amd/mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I42cc6686d8fa3f694a46ba4ca801a822ef1db1d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-09soc/amd/cezanne,picasso/include/southbridge: fix typo in defineFelix Held
In both the Picasso PPR (rev 3.16) and the Cezanne PPR (rev 3.03) bit 16 of the misc I2C pad control registers is defined as BiasCrtEn, so rename I2C_PAD_CTRL_BIOS_CRT_EN to I2C_PAD_CTRL_BIAS_CRT_EN. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If39ac17a433cb90c944fdde038cd246a995e193a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59028 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-09amd/sata: Remove the weak functionZheng Bao
BUG=b:140165023 Change-Id: I1908f727a7be1e33cbfd273b7261cbd989a414fe Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-08soc/amd/{cezanne,picasso}: Stop passing base for fspm.binRaul E Rangel
We no longer need to do this since we relocate at runtime. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibef849d5b3f0290cb7b7c5ff18aabe002bf53344 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-08soc/amd/cezanne: Enable CBFS_PRELOADRaul E Rangel
The follow up CLs will use CBFS_PRELOAD. The default CBFS_CACHE_SIZE was derived by examining the `cbfstool print` output and summing the files we intend to preload. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I208067e6ceec6ffb602a87bee3bf99a0a75c822d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-08soc/amd/picasso/include/southbridge: drop unused aoac_devs structFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ida8d767a5b56bdf59747362ddf68372436573895 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58972 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-08soc/amd/cezanne: Add ASYNC_FILE_LOADINGRaul E Rangel
This gives us a knob that can be controlled via a .config to enable/disable file preloading. I left the option disabled because there is currently a race condition that can cause data corruption when using the SPI DMA controller. The fix will actually introduce a boot time regression because the preloads are happening at the same time as the elog init. I want to keep preloading disabled for now until I get all the sequencing worked out. BUG=b:179699789 TEST=Boot guybrush and verify no preloading happens. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie839e54fa38b81a5d18715f190c0c92467bd9371 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-05soc/amd/*/include/smi: move NUMBER_SMITYPES definition to the topFelix Held
Since all other defines for the number of certain things are at the top of the file, move NUMBER_SMITYPES there as well to keep things consistent. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idfb599531d6cc382ab258bd1eae89e7b35fa9e79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-05soc/amd/*/include/smi: fix off-by-one in SCIMAPS definesFelix Held
SCIMAPS is the total number of SCI to GEVENT mappings. configure_scimap returns early when the scimap is greater or equal than SCIMAPS, so for SMITYPE_ACDC_TIMER it returned early without doing what was expected from it to do despite that being a valid value, so fix this off-by-one. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibaf8c5618ddbf0b8d4cd612a7f1347d8562bbfcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-04soc/amd/common/block/spi: Add prompt to SOC_AMD_COMMON_BLOCK_SPI_DEBUGRaul E Rangel
Makes it so I can enable SPI debugging without modifying the source. BUG=b:179699789 TEST=Add CONFIG_SOC_AMD_COMMON_BLOCK_SPI_DEBUG=y to my .config Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie3815e0398b5268874039196a625fc29dd3dc3d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04Kconfig,soc/amd/cezanne: Make COOP_MULTITASKING select TIMER_QUEUERaul E Rangel
This reduces the number of selects required in the SOC_SPECIFIC_OPTIONS. BUG=b:179699789 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7f1364fc269ea5ec17982bf750a164a3290adb0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMARaul E Rangel
AMD platforms require the destination buffer to be 64 byte aligned when using the SPI DMA controller. BUG=b:179699789 TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug $1 = {buf = 0x0, size = 0, alignment = 64, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0} Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec Reviewed-on: https://review.coreboot.org/c/coreboot/+/58707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
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