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authorFelix Held <felix-coreboot@felixheld.de>2021-12-14 23:34:33 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-12-15 22:40:08 +0000
commitfc373c7dac077397a24f0930b83b805fc21fa270 (patch)
tree519184d4a1d71efa7d71ce03af458fd14cbf73e6 /src/soc/amd
parent55dce1d55df554e684c87ab1baea9edfcb12aa09 (diff)
soc/amd/common/block/psp: move psp_notify_dram to psp_gen1.c
The MBOX_BIOS_CMD_DRAM_INFO PSP mailbox command is only available on the first generation of PSP mailbox interface and not on the second generation. The second generation of the PSP mailbox interface was introduced with the AMD family 17h SoCs on which the DRAM is already initialized before the x86 cores are released from reset. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97b29fdc4a71d6493ec63fa60f580778f026ec0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/common/block/include/amdblocks/psp.h2
-rw-r--r--src/soc/amd/common/block/psp/psp.c23
-rw-r--r--src/soc/amd/common/block/psp/psp_def.h4
-rw-r--r--src/soc/amd/common/block/psp/psp_gen1.c23
4 files changed, 27 insertions, 25 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h
index e749d75df1..c9986cae00 100644
--- a/src/soc/amd/common/block/include/amdblocks/psp.h
+++ b/src/soc/amd/common/block/include/amdblocks/psp.h
@@ -51,6 +51,8 @@ void soc_fill_smm_reg_info(struct smm_register_info *reg); /* v2 only */
#define PSPSTS_INVALID_NAME 8
#define PSPSTS_INVALID_BLOB 9
+/* PSP gen1-only. SoCs with PSP gen2 already have the DRAM initialized when
+ the x86 cores are released from reset. */
int psp_notify_dram(void);
int psp_notify_smm(void);
diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c
index b95545923f..66f7d59224 100644
--- a/src/soc/amd/common/block/psp/psp.c
+++ b/src/soc/amd/common/block/psp/psp.c
@@ -56,29 +56,6 @@ void psp_print_cmd_status(int cmd_status, struct mbox_buffer_header *header)
}
/*
- * Notify the PSP that DRAM is present. Upon receiving this command, the PSP
- * will load its OS into fenced DRAM that is not accessible to the x86 cores.
- */
-int psp_notify_dram(void)
-{
- int cmd_status;
- struct mbox_default_buffer buffer = {
- .header = {
- .size = sizeof(buffer)
- }
- };
-
- printk(BIOS_DEBUG, "PSP: Notify that DRAM is available... ");
-
- cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer);
-
- /* buffer's status shouldn't change but report it if it does */
- psp_print_cmd_status(cmd_status, &buffer.header);
-
- return cmd_status;
-}
-
-/*
* Notify the PSP that the system is completing the boot process. Upon
* receiving this command, the PSP will only honor commands where the buffer
* is in SMM space.
diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h
index 4d3aca59b3..5baa0642dc 100644
--- a/src/soc/amd/common/block/psp/psp_def.h
+++ b/src/soc/amd/common/block/psp/psp_def.h
@@ -8,7 +8,6 @@
#include <amdblocks/psp.h>
/* x86 to PSP commands */
-#define MBOX_BIOS_CMD_DRAM_INFO 0x01
#define MBOX_BIOS_CMD_SMM_INFO 0x02
#define MBOX_BIOS_CMD_SX_INFO 0x03
#define MBOX_BIOS_CMD_SX_INFO_SLEEP_TYPE_MAX 0x07
@@ -19,7 +18,8 @@
#define MBOX_BIOS_CMD_S3_DATA_INFO 0x08
#define MBOX_BIOS_CMD_NOP 0x09
#define MBOX_BIOS_CMD_ABORT 0xfe
-/* x86 to PSP commands, v1 */
+/* x86 to PSP commands, v1-only */
+#define MBOX_BIOS_CMD_DRAM_INFO 0x01
#define MBOX_BIOS_CMD_SMU_FW 0x19
#define MBOX_BIOS_CMD_SMU_FW2 0x1a
diff --git a/src/soc/amd/common/block/psp/psp_gen1.c b/src/soc/amd/common/block/psp/psp_gen1.c
index 55070f258d..37257ba92e 100644
--- a/src/soc/amd/common/block/psp/psp_gen1.c
+++ b/src/soc/amd/common/block/psp/psp_gen1.c
@@ -170,3 +170,26 @@ int psp_load_named_blob(enum psp_blob_type type, const char *name)
cbfs_unmap(blob);
return cmd_status;
}
+
+/*
+ * Notify the PSP that DRAM is present. Upon receiving this command, the PSP
+ * will load its OS into fenced DRAM that is not accessible to the x86 cores.
+ */
+int psp_notify_dram(void)
+{
+ int cmd_status;
+ struct mbox_default_buffer buffer = {
+ .header = {
+ .size = sizeof(buffer)
+ }
+ };
+
+ printk(BIOS_DEBUG, "PSP: Notify that DRAM is available... ");
+
+ cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer);
+
+ /* buffer's status shouldn't change but report it if it does */
+ psp_print_cmd_status(cmd_status, &buffer.header);
+
+ return cmd_status;
+}