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authorFelix Held <felix-coreboot@felixheld.de>2021-12-07 00:38:29 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-12-08 13:44:27 +0000
commit688f09f97ad5b25e3374653eebafbb5220032feb (patch)
tree4673e452e1a8757ad7c4b77b0641235c3be5c522 /src/soc/amd
parent09cdecec9c22a0cd63b1f7d7906b5abc78443064 (diff)
soc/amd/stoneyridge/southbridge: fix setting SPI_USE_SPI100
Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities of the SPI interface. The reference code for Stoneyrige also only sets the SPI_USE_SPI100 bit and doesn't zero out the other bits. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4d32fc2084bb34ea57924bae68511c6836587790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index de27ac540a..63bfd832b3 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -242,7 +242,7 @@ void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)
(fast << SPI_FAST_SPEED_NEW_SH) |
(alt << SPI_ALT_SPEED_NEW_SH) |
(tpm << SPI_TPM_SPEED_NEW_SH));
- spi_write16(SPI100_ENABLE, SPI_USE_SPI100);
+ spi_write16(SPI100_ENABLE, SPI_USE_SPI100 | spi_read16(SPI100_ENABLE));
}
static void sb_disable_4dw_burst(void)