diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-12-07 00:38:29 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-08 13:44:20 +0000 |
| commit | 09cdecec9c22a0cd63b1f7d7906b5abc78443064 (patch) | |
| tree | 5cff1645f785bc369f865021d34b74ee782babb0 /src/soc/amd | |
| parent | 9bfbcd2127bd7416c5ff90509aeeac91f20e27f9 (diff) | |
soc/amd/common/block/spi: fix setting SPI_USE_SPI100 in SPI100_ENABLE
Use a read modify write sequence when setting the SPI_USE_SPI100 bit in
the SPI100_ENABLE register. This avoids clearing other bits in the
register which might cause instabilities of the SPI interface. The
reference code for both Picasso and Cezanne also only sets the
SPI_USE_SPI100 bit and doesn't zero out the other bits.
TEST=Verified that Mandolin still boots. It didn't show any signs of
possibly related instabilities before though, so this test doesn't say
much.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I71c2ec1729d5cb4cdff6444b637af29caaa6f1c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/block/spi/fch_spi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index fad8cd9951..5ef900c3c5 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -74,7 +74,7 @@ static uint8_t lower_speed(uint8_t speed1, uint8_t speed2) static void fch_spi_set_spi100(uint8_t norm, uint8_t fast, uint8_t alt, uint8_t tpm) { spi_write16(SPI100_SPEED_CONFIG, SPI_SPEED_CFG(norm, fast, alt, tpm)); - spi_write16(SPI100_ENABLE, SPI_USE_SPI100); + spi_write16(SPI100_ENABLE, SPI_USE_SPI100 | spi_read16(SPI100_ENABLE)); } static void fch_spi_configure_4dw_burst(void) |