diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-11-05 10:29:24 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-11-08 19:58:57 +0000 |
| commit | 6fd23cb2d249e44b6e7e86bd6b95bdba9992f3db (patch) | |
| tree | 42b7ad60a759a0aa0782deb99cf31843a467ba31 /src/soc/amd | |
| parent | 4911dc7ca90cfe758227e7a86b8c950a48c6ff6e (diff) | |
soc/amd/{cezanne,picasso}: Stop passing base for fspm.bin
We no longer need to do this since we relocate at runtime.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibef849d5b3f0290cb7b7c5ff18aabe002bf53344
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/Makefile.inc | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 87874418c3..8db0f6cd8d 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -53,8 +53,6 @@ CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include CPPFLAGS_common += -I$(src)/soc/amd/cezanne/acpi CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne -$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) - MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR) # ROMSIG Normally At ROMBASE + 0x20000 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 45e9c80330..7db4719db6 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -281,8 +281,6 @@ apu/amdfw_b-position := $(call strip_quotes, $(CONFIG_PICASSO_FW_B_POSITION)) apu/amdfw_b-type := raw endif -$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) - cpu_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/UcodePatch_*.bin) endif # ($(CONFIG_SOC_AMD_PICASSO),y) |