diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-11-25 19:53:37 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-29 20:46:12 +0000 |
| commit | f6205d3deb8f0b2f22cb2ccc8d708312aeb2c8fa (patch) | |
| tree | e5186467a1c8410eebef6ba01c050fdd487bc704 /src/soc/amd | |
| parent | 8c4fe3f0f66f27a5657db472d7114ab2af19d8ed (diff) | |
soc/amd/common/block/lpc: use 32 bit accesses in lpc_enable_port80
When using 32 bit PCI accesses in lpc_enable_port80, we can use the
LPC_IO_OR_MEM_DECODE_ENABLE and DECODE_IO_PORT_ENABLE4 defines and don't
need to re-define bits with offsets from the beginning of the third byte
within this 32 bit register. This allows to drop the
LPC_IO_OR_MEM_DEC_EN_HIGH register definition which points to
LPC_IO_OR_MEM_DECODE_ENABLE + 2 and to drop the re-definitions of the
bit re-definitions with a different offset.
The code in lpc_enable_port80 was originally copied from sb/amd/agesa/
hudson/early_setup.c which might be sort-of a copy from what the AGESA
reference code does.
TEST=When commenting out SOC_AMD_COMMON_BLOCK_USE_ESPI in the Kconfig of
Mandolin and selecting AMD_LPC_DEBUG_CARD, all POST codes still get
shown on the POST code LED display when this patch is applied.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I001bb1c2ccf99e36d4fbd73d3bf96b78ddb87d67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/lpc.h | 12 | ||||
| -rw-r--r-- | src/soc/amd/common/block/lpc/lpc_util.c | 8 |
2 files changed, 4 insertions, 16 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 024d479561..c5f3c78821 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -67,18 +67,6 @@ #define LPC_SELECT_SIO_2E2F 0 #define WIDEIO_RANGE_ERROR -1 -/* Assuming word access to higher word (register 0x4a) */ -#define LPC_IO_OR_MEM_DEC_EN_HIGH 0x4a -#define LPC_WIDEIO2_ENABLE_H BIT(9) -#define LPC_WIDEIO1_ENABLE_H BIT(8) -#define DECODE_IO_PORT_ENABLE6_H BIT(7) -#define DECODE_IO_PORT_ENABLE5_H BIT(6) -#define DECODE_IO_PORT_ENABLE4_H BIT(5) -#define DECODE_IO_PORT_ENABLE3_H BIT(3) -#define DECODE_IO_PORT_ENABLE2_H BIT(2) -#define DECODE_IO_PORT_ENABLE1_H BIT(1) -#define DECODE_IO_PORT_ENABLE0_H BIT(0) - #define LPC_MEM_PORT1 0x4c #define ROM_PROTECT_RANGE0 0x50 #define ROM_BASE_MASK 0xfffff000 /* bits 31-12 */ diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index c40a198493..72919598a3 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -138,11 +138,11 @@ int lpc_set_wideio_range(uint16_t start, uint16_t size) void lpc_enable_port80(void) { - u8 byte; + uint32_t tmp; - byte = pci_read_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); - byte |= DECODE_IO_PORT_ENABLE4_H; - pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); + tmp = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); + tmp |= DECODE_IO_PORT_ENABLE4; + pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, tmp); } void lpc_enable_sio_decode(const bool addr) |