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2024-07-12soc/intel/cmn/cse: Correct CMOS error message for CSE partition firmwareSubrata Banik
The CMOS entry for CSE partition firmware was incorrectly labeled as `ramtop` and `partition firmware` in the error messages. This patch corrects the messages to accurately refer to `CSE partition firmware`. Additionally, the alignment and size check comments are updated to reflect this change. Change-Id: Ib3a7fb88f52c4d0c47d828bcd1c4649e62d19654 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-11soc/intel/cmn/cse: Refine boot partition loggingSubrata Banik
This patch ensures CSE boot partition (RO/RW) version information only log when the status is "success". If the status is not successful, log an error message indicating the failure and status code. This change avoids logging potentially incorrect version information when the boot partition is not valid. BUG=b:305898363 TEST=Builds successfully for google/rex variants. Change-Id: I1932302b145326a1131d64b04af1cbfd6d050b7b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-11soc/intel/meteorlake: Conditional selection of CSE Lite PSRSubrata Banik
This patch makes the selection of `SOC_INTEL_CSE_LITE_PSR` conditional on both `MAINBOARD_HAS_CHROMEOS` and `SOC_INTEL_CSE_LITE_SKU` being enabled. This ensures that CSE Lite PSR is only active when both ChromeOS is the target platform and CSE sync is performed inside coreboot. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I7199c034bbe6e7f077650417da67fa544f0b49d5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83396 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-11soc/intel: Extend CSE RW Update and ME read access for payload syncSubrata Banik
Modify the dependencies for `SOC_INTEL_CSE_RW_UPDATE` and `ME_REGION_ALLOW_CPU_READ_ACCESS` config options to include `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD`. This allows these features to be enabled even when CSE sync is performed in the payload, not just within coreboot (when `SOC_INTEL_CSE_LITE_SKU` config is enabled). BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Id6ec19d74237f278e8383c89923523871b2cc2db Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-11soc/intel/meteorlake: Conditionally update CSE sync UPDs in FSP-MSubrata Banik
This patch updates FSP-M UPDs conditionally to ensure CSE firmware updates and VGA initialization control only when `SOC_INTEL_CSE_LITE_SKU` config is enabled. This ensures eSOL rendering is tied to CSE sync performed in coreboot, preventing unnecessary setup when sync is deferred to the payload. Deferring CSE sync to the payload results in the depthcharge screen. BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Iffdd4b1be4abba8c57e28542058a575cc6de674c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-11soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibilitySubrata Banik
This patch refactors the handling of CSE CBMEM IDs to enable platforms to choose whether to perform CSE sync operations within coreboot or defer it to the payload. This separation improves code organization, ensuring `cse_lite.c` focuses on coreboot-specific CSE Lite tasks. Now, platforms can select: * `SOC_INTEL_CSE_LITE_SKU` for CSE sync within coreboot * `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` for deferred payload sync This change ensures mutually exclusive options, avoiding unnecessary SPI flash size increases. BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83393 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-10cbmem_top: Change the return value to uintptr_tElyes Haouas
Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82752 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdtShuo Liu
Domain device objects are created with HID/CID/UID/_OSC/_PXM Dynamic domain SSDT generation could benefit the support of SoCs with multiple SKUs, or the case where one set of codes supports multiple SoCs. One possible side-effect might be the extra performance cost for generating these tables, which should not bring big impact on high performance server CPUs. GNR codes run with dynamic domain SSDT generation to fit for both GraniteRapids and SierraForest SoCs. TEST=Build on intel/avenuecity CRB TEST=Build on intel/beechnutcity CRB Change-Id: I28bfdf74d8044235f79f67d832860d8b4306670c Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-07-03soc/intel/xeon_sp/gnr: Support fast bootGang Chen
Fast boot will used pre-saved hardware configuration data to accelerate the boot process, e.g. DDR training is skipped by using pre-saved training data. Enable fast boot on cold and warm resets by default. Change-Id: Ib5dc76176b16ea1be5dd9b05a375c9179411f590 Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-07-03soc/intel/common: Skip ME version log for Lite SKUSubrata Banik
This change skips the ME firmware version logging in print_me_fw_version() if the ME firmware SKU is detected as Lite SKU. The reasoning is that the RO (BP1) and RW (BP2) versions are already logged by the cse_print_boot_partition_info() function for Lite SKUs, making the additional log redundant. The check for the Lite SKU has been moved to print_me_fw_version(), where the decision to print the version is made, instead of in get_me_fw_version(), where the version information is retrieved. TEST=Able to build and boot google/rex. w/o this patch: [DEBUG] ME: Version: Unavailable w/ this patch: Unable to see such debug msg. Change-Id: Ic3843109326153d5060c2c4c25936aaa6b4cddda Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-03soc/intel/cmn/cse: Make ME firmware version query function staticSubrata Banik
This change modifies the get_me_fw_version() function to be statically scoped within src/soc/intel/common/block/cse/cse.c, as it is only used by the print_me_fw_version() function in the same file. The function declaration is also removed from intelblocks/cse.h. The order of the function definitions in cse.c was also changed to be more logical, with the now static helper function get_me_fw_version() defined first, before it is used. TEST=Able to build google/rex. Change-Id: Idd3a6431cfa824227361c7ed4f0d5300f1d04846 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83257 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03soc/intel/cmn/cse: Conditionally disable ME status reportingSubrata Banik
This patch disables the ME status reporting functionality (dump_me_status, print_me_fw_version) in the CSE driver when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is defined. This is likely intended for platforms or configurations where the CSE communication is only limited to payload. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I5e360408a7847968117df475ff244d79ceafa23f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83233 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-03soc/intel/cmn/cse: Skip CSE version call if sync is done by payloadSubrata Banik
This patch skips the CSE firmware version print when CSE sync is done by payload. The payload is responsible to dump the CSE version. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I1a9e5583c79ebd81291a4b3ae24529b4582502cb Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-03soc/intel/cmn/cse: Modify dependency on CSE EOP configsSubrata Banik
Refactor CSE lite End-of-Post (EOP) configs to support the alternative of sending CSE communication from the payload. When the SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD config is selected, coreboot will skip initiating CSE EOP operations and rely on the payload CSE driver implementation. The following configs are modified to ensure coreboot skips CSE communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled: - SOC_INTEL_CSE_SEND_EOP_EARLY - SOC_INTEL_CSE_SEND_EOP_LATE - SOC_INTEL_CSE_SEND_EOP_ASYNC - SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD BUG=b:305898363 TEST=Able to build google/rex. Change-Id: Ia6b616163d02be8d637b134fd3728c391fc63c90 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83229 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03soc/intel/cmn/cse: Modify dependency on CSE lite configsSubrata Banik
Refactor CSE lite configs (specifically CSE sync related) to support the alternative of sending CSE communication from the payload. When the SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD config is selected, coreboot will skip initiating CSE sync operations and rely on the payload CSE driver implementation. The following configs are modified to ensure coreboot skips CSE communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled: - SOC_INTEL_CSE_LITE_PSR - SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY - SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE - SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I5ddaf6e29949231db84b14bf7ea2d34866bb8e6c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83228 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-03tree: Use <console/console.h> only when usedElyes Haouas
Change-Id: I3cb1f11beba61afdf2be6188bde9ff135f8ace50 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-07-023rdparty/fsp: Update submodule to upstream masterFelix Singer
The filename of the Elkhart Lake FSP binary changed in the FSP repository. It's unlikely that it will be renamed to the original name soon. Thus, update the filename in the coreboot repository. Updating from commit id cc6399e: 2024-03-04 15:40:41 +0800 - (IoT MTL-UH & MTL-PS PV (3471_49) FSP) to commit id 800c857: 2024-06-25 15:47:28 +0800 - (Update Fsp.fd) This brings in 23 new commits: 800c857 Update Fsp.fd 41e4590 NEX AZB IPU24.4 (5254_00) FSP 0efd8a3 IoT RPL-PS PV (5045_47) FSP 196e3fe Update README.md 380afd8 Update README.md 5dc88ca NEX ADL-PS IPU24.3/MR6 (5045_02) FSP 22762e9 Merge branch 'master' of https://github.com/intel/FSP 8134dbd Elkhart Lake IPU2024.3 FSP 3819544 add required SECURITY.md file for OSSF Scorecard compliance a6ee963 Delete AlderLakeFspBinPkg.dec 9d819ea Deprecate Client/AlderLakeFspBinPkg f963690 Raptor Lake FSP C.1.C8.50 f67f9ef Raptor Lake FSP C.0.C8.50 68c3cfa NEX ADL-PS IPU 2024.3 (5045_02) FSP f0d04d9 NEX ADL-P IPU 2024.3 (5045_02) FSP 6fa139c NEX ADL-S IPU 2024.3 (5045_02) FSP c4af5ac NEX TGL IPU 2024.3 (7092_01) FSP 8cf0372 IoT ADL-N MR4 (5061_00) e5ceb0b Merge branch 'master' of https://github.com/intel/FSP aada6a5 Elkhart Lake IPU2024.2 FSP 90d1d3b Update README.md 1a5a3ee Testing 61c069a NEX RPL-S MR3 (4445_03) FSP Change-Id: I47013bce65054f2c496c9aa7c16e55b51d65e5fe Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83294 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28device/azalia_device.c: Always read-write GCAPAngel Pons
In the HD Audio Specification Rev. 1.0a, every bitfield in the GCAP register is RO (Read Only). However, it is known that in some Intel PCHs (e.g 6-series and 7-series, documents 324645 and 326776), some of the bitfields in the GCAP register are R/WO (Read / Write Once). GCAP is RO on 5-series PCHs; 8-series and 9-series PCHs have a lock bit for GCAP elsewhere. Lock GCAP by reading GCAP and writing back the same value. This has no effect on platforms that implement GCAP as a RO register or lock GCAP through a different mechanism. Change-Id: Id61e6976a455273e8c681dbeb4bad35d57b1a8a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-28soc/intel/xeon_sp: Reserve MMIO for Gen1 SoCShuo Liu
For Gen1 SoCs, the range starting from the end of VTd BAR to the end of 32-bit domain MMIO resource window is reserved for unknown devices. Get them reserved. TEST=Build and boot on intel/archercity CRB Change-Id: Ie133fe3173ce9696769c7247bd2524c7b21b1cf8 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-28soc/intel/xeon_sp: Reserve MMIO range for VTd BAR dynamicallyShuo Liu
vtd_probe_bar_size is used to decide the BAR size. TEST=Build and boot on intel/archercity CRB Change-Id: Ie45dd29e386cbfcb136ce2152aba2ec67757ee3c Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82431 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26acpi: Rename acpi_create_dmar_drhdShuo Liu
For most of SoCs, DRHD is by default with the size of 4KB. However, larger sizes are allowed as well. Rename acpi_create_dmar_drhd to acpi_create_dmar_drhd_4k to support the default case while a later patch will re-add acpi_create_dmar_drhd with a size parameter. TEST=intel/archercity CRB Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-25soc/intel/common: Extend WAIT_FOR_DP_MODE_ENTRY_TIMEOUT_MS to 1500msTony Huang
Some dongles require more time to be ready, this CL extedns the DP mode entry timeout from 0.5s to 1.5s and make sure the tested dongle display works. Before: [WARN ] DP not ready after 500ms. Abort. After: [INFO ] DP ready after 1211 ms BUG=b:348309582 TEST=emerge coreboot verify tested dongles and monitors display works Change-Id: I22d7800b50f6f7de9f147ae6998a5015d0dc0be9 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83206 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-06-23skl mainboards: Move cpu_cluster device to chipset devicetreeFelix Singer
Change-Id: I7114612e686a0bf3cfc241f45fa62077fad16f5a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-21soc/intel/cmn/block/cse: Create CBMEM entries for payload to fill with CSE infoKapil Porwal
Currently, the payload cannot create new CBMEM entries as there is no such infrastructure available. The Intel CSE driver in the payload needs below CBMEM entries - 1. CBMEM_ID_CSE_INFO to - a. Avoid reading ISH firmware version on consecutive boots. b. Track state of PSR data during CSE downgrade operation. 2. CBMEM_ID_CSE_BP_INFO to avoid reading CSE boot partition information on consecutive boots. The idea here is to create required CBMEM entries in coreboot so that later they can be consumed by the payload. BUG=b:305898363 TEST=Store CSE version info in CBMEM area in depthcharge on Screebo Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I9561884f7b9f24d9533d2c433b4f6d062c9b1585 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83103 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21soc/intel/cmn/acpi: Add support for `PCR_BASE_ADDRESS` above 4 GiBSubrata Banik
This change updates the Northbridge ASL to conditionally include a QWordMemory resource for `SM01` when the `CONFIG_PCR_BASE_ADDRESS` is above 4 GiB. If `CONFIG_PCR_BASE_ADDRESS` is below 4 GiB, or falls within the PCH reserved range, the existing handling of `SM01` remains unchanged (as a DWordMemory resource). TEST=Built with CONFIG_PCR_BASE_ADDRESS both above and below 4 GiB, verified ASL output. Change-Id: I9547377cdea6cb4334ab59b3bc837059fbb22e3b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83112 Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-16soc/intel/alderlake: Use the RPL-P IoT FSP if desiredBenjamin Doron
This change also drops a duplicated config default line, which might be why this was omitted. Change-Id: I2b4c8b316adaadec3e49d5162b37b37629331b06 Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83086 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-14soc/intel/common/block: Move VTd basic definitions into header fileJincheng Li
TEST=Build and boot on intel/archercity CRB Change-Id: I4f9e606cf9ec01ec157ef4dd7c26f6b5eb88c7b7 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82941 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-13soc/intel/adl: Skip RW CBFS ucode update if RO is lockedSubrata Banik
This patch eliminates coreboot from loading microcode from RW CBFS (when the RO descriptor is locked, which indicates a fixed RO image) because the kernel can already patch the microcode on BSPs and APs while booting to OS. This may be a chance to lower the burden on the AP FW side because patching microcode on in-field devices is subject to firmware updates, which are rarely published and, if required, must go through the firmware qualification testing procedure (which is costly, unlike kernel updates for ucode updates). 1. The FIT loads the necessary microcode from the RO during reset. 2. Reloading microcode from RW CBFS impacts boot time (~60ms, core-dependent). 3. The kernel can still load microcode updates. ChromeOS devices leverage RO+RW-A/RW-B booting. The RO's microcode is sufficient for initial boot, and the kernel can apply updates later. BUG=none TEST=Verified boot optimization; in-field devices skip RW-CBFS microcode loading when RO is locked. Change-Id: I68953d45d3624aba0a3be28bc7b266b7621ddcc4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82999 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-13soc/intel/apollolake: Add SoC-specific microcode update check for GLKMatt DeVillier
While both APL and GLK load the CPU microcode from FIT, only GLK supports the PRMRR/SGX feature. When this feature is supported, the FIT microcode load will set the msr (0x08b) with the patch id/revision one less than the revision in the microcode binary. This results in coreboot attempting (and failing) to reload the microcode again in ramstage. Avoid the microcode reload attempt for GLK by using a SoC- specific microcode update check which accounts for the off-by-1 when comparing versions. Implementation is based on the one used for SKL and CNL, but modified based on feedback in comments on Gerrit. TEST=build/boot google/reef (electro) and google/octopus (ampton), verify in cbmem console log that CPU microcode update in ramstage is skipped due to already being up to date, and that GLK uses the SoC-specific check and APL uses the non-specific/general one. Change-Id: Iab97f23d4388d5057797bb13f585db821c735bd0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83037 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetreeMichał Żygowski
The UsbTcPortEn UPD for FSP-S is being set in ramstage, however the equivalent FSP-M UPD, the UsbTcPortEnPreMem, was not being set. Following the Meteor Lake example, set the UsbTcPortEnPreMem UPD as well for Alder Lake. Setting this FSP-M UPD will cause FSP to properly program sideband use BSSB_LSx pins for the enabled Type-C ports. Required for proper DCI debug and TCSS initialization flow. Change-Id: If3b79167ec1769ddfb7d28a6c78a3e80bd10afe7 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80500 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-07soc/intel/cmn/cse: Support CSE sync from payloadKapil Porwal
Skip CSE sync in coreboot when payload is doing it. BUG=b:305898363 TEST=Verify CSE sync from depthcharge on Screebo Change-Id: Ifa942576c803b8ec9e1e59c61917a14154fb94b2 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-06-07soc/intel/common/uart: Drop chip in favor of devicetree opsArthur Heymans
It is now possible to hook up device ops directly to devices in devicetree which removes the need for a fake chip. This also fixes Hermes booting as the PCI ops were incorrectly hooked up to a dummy device. The intel uart driver was requesting a resource from the generic device and died since it does not exist: [EMERG] GENERIC: 0.0 missing resource: 10 This was broken in commit b9165199c32a (mb/prodrive/hermes: Rework UART devicetree entry). Change-Id: I3b32d1cc52afaed2a321eea5815f2957fe730f79 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82940 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-07soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSIONRonak Kanabar
This patch introduces support for storing the MRC cache based on the MRC version for both ADL-N and TWL platforms. It select the MRC_CACHE_USING_MRC_VERSION option when client SOC_INTEL_ALDERLAKE_PCH_N is chosen. BUG=b:296433836 Change-Id: Icc7e4ecd84a7d2818d54acc6ac5d0592544bb9ce Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81038 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Brandon Weeks <bweeks@google.com>
2024-06-07intel/alderlake/Kconfig: Use vendorcode headers for Client ADL-N FSPRonak Kanabar
This patch is to switch Client ADL-N FSP headers to vendorcode from IOT headers. Also guard IOT headers & bin path with FSP_TYPE_IOT Kconfig. BUG=b:296433836 TEST=Able to build and boot google/nivviks Change-Id: I1ffcc3f284c213ff0533de3a0e228aacf523b380 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-07soc/intel/alderlake: Guard PchPcieClockGating & PchPciePowerGating UPDsRonak Kanabar
PchPcieClockGating & PchPciePowerGating UPDs are not available for ADL_N FSP headers. Add guard to Avoid PchPcieClockGating & PchPciePowerGating programming for ADL_N FSP. Change-Id: I2f1625038896b07c354498fe431cad97fb9b5bdb Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82917 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-05cpu/x86: Make 1GB paging the defaultJulius Werner
This patch flips the polarity of CONFIG_USE_1G_PAGES_TLB into CONFIG_NEED_SMALL_2MB_PAGE_TABLES which is off by default, meaning CPUs added in the future will automatically build the smaller 1GB pages. We can expect support for this feature to be available on all future CPU generations (with the possible exception of embedded edge cases), so this default setting should make mistakes less likely and keep maintenance effort lower. (Besides, enabling the support where it doesn't work fails fast, whereas keeping it disabled where it could work is an inefficiency that can easily go overlooked for a long time.) While this is technically a CPU feature, not a northbridge feature, we support a lot more individual CPUs than northbridges in the pre-SoC era, and they tend to be closely coupled anyway. So select the option at the northbridge level for older CPUs to keep things simpler. Change-Id: I2cf1237a7fb63b8904c2a3d57fead162c66bacde Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-05soc/intel/xeon_sp: Remove duplicated Kconfig POSTCAR_STAGEJincheng Li
POSTCAR_STAGE is already selected in XEON_SP_COMMON_BASE Change-Id: I3f94e6cc76c8f376119ffa8ec43fa1a43fb40977 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82795 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-06-04soc/intel/xeon_sp: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: I950b8859b51fb61edc0cf1115f6665378bc0b836 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82887 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-03tree: Use calloc(n, sizeof(struct)) insteadof calloc(sizeof(struct), n)Elyes Haouas
Change-Id: I5e67e370d4eb8fe28227843bbca34db06ad84b26 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82786 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-03soc/intel/meteorlake: Enable USB2 port reset message on Type-C portsJeremy Soller
Apply commit c6b65c1a811e ("soc/intel/alderlake: Enable USB2 port reset message on Type-C ports") to Meteor Lake. This change is added to address the issue of USB3 ports downgrading to high speed during low power modes and not returning back to super speed. The patch enables port reset event on USB2 ports. This event is is passed to USB3 upstream ports to upgrade back to super speed (USB3) after a downgrade during low power state. Change-Id: Iac702a8d8edd2b3b7e03abcac020be7e45335821 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82730 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-03soc/intel/meteorlake: Hook up PchHdaAudioLinkHdaEnable to devicetreeMichał Kopeć
The comment that the PchHdaAudioLink UPDs only configure GPIOs is incorrect. Setting this to 1 is needed to enable HDA audio link. Same exact situation as with Alder Lake in CL 71715. Change-Id: Iecbe106ae18b5a8b53c04a5335a4e4c4ae27c7a0 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2024-05-31soc/intel: Fix pointer size mismatch errors in crashlogAppukuttan V K
The crashlog code in intel/common/block and meteorlake soc was casting integer addresses directly to pointer types, which caused compilation errors in x86_64 bit builds. This commit fixes the issue by using uintptr_t for casting integer addresses to pointer types before dereferencing. BUG=b:329034258 TEST=Successfully build Meteor Lake (rex) in both x86_32 and x86_64 modes. Change-Id: I2d0814a8b767270ec140341bfb51d0782469545d Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82481 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-31soc/intel/xeon_sp: Add _OSC ASL generation utils for IIO domainsShuo Liu
For multi-SKU/SoC supports, IIO domain layouts are returned from FSP HOBs. Add _OSC ASL generation utils so that static IIO domain layout definition file per SKU/SoC are not needed any more. The _OSC generation codes is a thin AML generation layer which further invokes \_SB.POSC which is defined in ASL. The ASL handler is able to handle boot-time generated info as parameters while keeps good readability for the ease of maintenance. In this case, firmware granted capabilities are calculated in boot time and passed to ASL handler as parameters. TEST=Build and boot on intel/archercity CRB Change-Id: Ibd3bfa2428725fe593754436d5ed75a3a11b4cdc Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2024-05-31soc/intel/meteorlake: Exclude deprecated upd from FSP2.4 buildsAppukuttan V K
EnableMultiPhaseSiliconInit upd is deprecated and has been removed starting with v2.4 of FSP specification. Multi-phase silicon initialization is mandatory for all FSP implementations compliant to v2.4. The following modifications are made: - In fsp_params.c and silicon_init.c EnableMultiPhaseSiliconInit update is guarded so that it will get included only if FSP2.4 is not selected. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Icdbf3bacc0a05975fc941b264fd400d74f506fce Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-31soc/intel/meteorlake: Tailor FSP Version Selection for ArchitectureSubrata Banik
* Conditionally select FSP 2.4 when x86_64 support is available (HAVE_X86_64_SUPPORT). * Default to FSP 2.3 otherwise. * Adjust default FSP header path to align with architecture. BUG=b:242829490 TEST=Able to build google/rex in both 32-bit and 64-bit mode. Change-Id: Ib77a34c6bf7bca3485a197f109d1550ac3d51cc0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-31soc/intel/meteorlake: Enable eSOL without 64-bit supportSubrata Banik
This change allows eSOL to be enabled on production Meteor Lake silicon even when 64-bit support is not present. eSOL support is still TBD for 64-bit FSP hence, skip adding this support for 64-bit build. TEST=Able to build and boot google/rex64 w/o eSOL. Change-Id: I16762e5b74ae0aaa3c28730479a1fd9defc4d93c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82716 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-30vc/intel/fsp/mtl: Add x86_64 FSP V3471.91 headersAppukuttan V K
This commit introduces new header files of V3471.91 for the x86_64 architecture in the fsp2_0/meteorlake directory. FSP2.4 brings FSP 64-bits support and the soc Kconfig file has been updated to select this new header path when FSP2.4 is in use. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Ib41b57e794311db729ac65a968f562aa127e86c3 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-05-30vc/intel/fsp/mtl: Organize FSP headers into x86_32 directoryAppukuttan V K
This commit moves FSP V3471.91 header files for Meteor Lake into a new x86_32 directory to better organize the files based on the architecture. The Kconfig file has been modified accordingly to reflect the new paths of the relocated headers. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Id30186a8b1b5a9082f498e18a3378f5e9907b668 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82424 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-30soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibilityAppukuttan V K
This commit updates the type definitions for FSP parameters in the Meteor Lake platform to ensure compatibility with the FSP2.4 specification, that supports 64-bit builds for the first time and this also ensures that parameter types works for both 32-bit and 64-bit builds. - In fsp_params.c, FSPS_ARCH_UPD macro is changed to FSPS_ARCHx_UPD which supports FSP2.4 and older specifications. Special handling is added for FspEventHandler assignment to handle as the variable type is different in both cases. - In meminit.c, the type for SPD pointers is changed from uint32_t to efi_uintn_t to support both 32-bit and 64-bit builds. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Ide220f60184135a6488f4472f69a471e2b383e2a Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82177 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29tree: Use <stdio.h> for snprintfElyes Haouas
<stdio.h> header is used for input/output operations (such as printf, scanf, fopen, etc.). Although some input/output functions can manipulate strings, they do not need to directly include <string.h> because they are declared independently. Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-28soc/intel/xeon_sp: Add PD_TYPE_CLUSTERShuo Liu
Add a new proximity type to represent the sub-NUMA cluster (SNC). This patch adds necessary Xeon-SP common code level support for SNC support. When SNC on, each SNC cluster will have a proximity domain. DIMMs and CPU cores are attached to SNC proximity domains instead of the processor proximity domains. With SNC, there are 3 types of proximity domains, PD_TYPE_PROCESSOR, PD_TYPE_GENERIC_INITIATOR and PD_TYPE_CLUSTER. proximity domain type checks in Xeon-SP codes are updated to correctly handle the adding of the new type. This patch doesn't actually enable SNC. To fully enable SNC, SoC codes need to override soc_get_cluster_count(), soc_set_cpu_node_ id() and memory_to_pd(), and call soc_set_cpu_node_id() in its per-CPU init routine. Change-Id: I32558983780f302ff4893901540a90baebf47add Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Ziang Wang <ziang.wang@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-28soc/intel/xeon_sp: Add domain resource window creation utilsShuo Liu
It might be benefical to have utils for domain resource window creation so that the correct IORESOURCE flags used could be guaranteed. TEST=Build and boot on intel/archercity CRB TEST=Build on intel/avenuecity CRB Change-Id: I1e90512a48ab002a1c1d5031585ddadaac63673e Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-05-24soc/intel/xeon_sp: Move get_cxl_mode out of soc/util.hShuo Liu
get_cxl_mode() is the interface for CXL mode config check used by SoC codes. It could be implemented by mechanisms outside of the SoC codes, e.g. board codes or OCP VPD driver. Move the interface declaration out of soc/util.h to a dedicated header, a.k.a., soc/config.h, so that the implementation codes do not need to include soc/util.h where there are lots of irrelevant definitions. Future SoC config check interfaces could be added to soc/config.h as well. The default weak implementation is moved out of util.c to config.c as well. TEST=Build and boot on intel/archercity CRB Change-Id: Ia0302b0d3fd93c49e1d6f64e8159f59d50f33e20 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82293 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23soc/intel/xeon_sp/gnr/soc_iio: Remove unused <string.h>Elyes Haouas
Change-Id: I8d4500edaa0739921831a3b04131046599c35a87 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-05-23soc/intel/xeon_sp: Dump proximity domain info per typesShuo Liu
Some proximity domain info are type specifics, e.g. base/size/dev are effective for PD_TYPE_GENERIC_INITIATOR, but not for PD_TYPE_PROCESSOR. Dump info per their type. TEST=Build and boot on intel/archercity Change-Id: I7e722a0577bba954efba3e91cc152c758c001d68 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-05-23soc/intel/xeon_sp: Move proximity domain setting upShuo Liu
Move proximity domain setting up to ahead of attach_iio_stacks() so that proximity domain info could be ready before attach_iio_stacks()/create_xeonsp_domains(). For example in SPR, is_iio_cxl_stack_res() refers to proximity domain info, and it will be called in create_xeonsp_domains(). TEST=Build and boot on intel/archercity No significant boot log difference except for proximity domain dump info display are moved ahead (with correct contents). Change-Id: I594f0ec0c23e3b62c3bdd917ebf6e45be6e4069e Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82267 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-21soc/intel/meteorlake: Add PsysPL2 configurationTony Huang
psys_pl2_watts is configured in SoC node of devicetree. Value represents Watts. BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot Change-Id: I9c4d62b93fc751db9e0ea04e475acb8861a844f8 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-16soc/intel/xeon_sp/gnr: Add IIO config utilsGang Chen
Add IIO configuration utils shared in GNR boards to handle the complex IIO configuration settings. Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690 Signed-off-by: Gang Chen <gang.c.chen@intel.com> Co-authored-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-14soc/intel/xeon_sp: Add Granite Rapids initial codesShuo Liu
coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single IO-APIC Xeon-SP platform. The same set of codes is also used for SRF (Sierra Forest) SoC. This patch initially sets the code set up as a build target with Granite Rapids N-1 FSP (src/vc/intel/fsp/fsp2_0/graniterapids). 1. All register definitions are forked from SPR (Sapphire Rapids) and EBG (Emmitsburg PCH)'s codes are reused. 2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later. Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Co-authored-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-14soc/intel/common: Add RPL tracehub supportAshish Kumar Mishra
Add PCI ID for RPL tracehub and update the PCI ID in the pci_device_ids[] in tracehub.c. Reference: Raptor Lake External Design Specification Volume 1 (640555) BUG=None TEST=Verified on brox Change-Id: I5d5c6c8ff44bcb5a7bbbd3e27a1577c169ecd6a9 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-05-14soc/intel/common: Add Panther Lake DIDsSaurabh Mishra
Reference: Panther Lake External Design Specification Volume 0.51 (815002) BUG=b:329787286 TEST=verified on Panther Lake Simics Platform. Change-Id: I941d6e1c8a697234b8e64a2523e60587897d7f7a Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81848 Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13soc/intel/xeon_sp: Use <spd.h>Elyes Haouas
Change-Id: Ib86df42c74474ab6d0bd389073c36ca0761748af Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-05-12soc/intel/lunarlake: Support stepping A0_2Saurabh Mishra
Details: - Add support for new Lunar Lake MCH ID 0x6410 - Add new CPU id 0xb06d1 Reference: Lunar Lake External Design Specification Volume 1 (734362) TEST=Build, boot the system and verfiy MCH-ID prints in bootblock stage. Below prints verified on Lunar Lake RVP board (lnlrvp). [DEBUG] MCH: device id 6410 (rev 02) is LunarLake M Change-Id: I976d7f269485633d835d204afa224736d71baaa8 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81847 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-12soc/intel/common: Add Lunar Lake CNVI device IDsSaurabh Mishra
Without this patch, ACPI SSDT does not supports and lists CNVW. With this patch, verified "CNVW" in ACPI SSDT listing. Scope (\_SB.PCI0) { Device (CNVW) { Name (_ADR, 0x0000000000140003) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Reference: Lunar Lake External Design Specification Volume 1 (734362) BUG=b:329787286 TEST=verified on Lunar Lake RVP board (lnlrvp). Change-Id: I5a0a3fbc9f43a6a573e33fcf3901055e10faaed1 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81846 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-09mb/google/brox: Sending End of Post (EOP) asynchronouslyKarthikeyan Ramasubramanian
Currently EOP message is sent to CSE late in the boot flow. Instead send it asynchronously to save ~10 ms in boot time. BUG=b:337330958 TEST=Build Brox BIOS Image and boot to OS. Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-08soc/intel/xeon_sp/spr: Refine return value checksShuo Liu
mp_init_with_smm returns cb_err type, where 0 means success and negative values represent error (see cb_err.h). However, failure checks in form of "ret < 0" is not straightforward. Use "ret != CB_SUCCESS" instead. Change-Id: I7e57f2da0361f3109051e9a35b1cce81d559b261 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-07soc/intel/meteorlake: Determine TBT controllers exist by VID/DIDKane Chen
The original code uses TRE0-TRE3 register to determine whether or not the TBT controller exists. However, there is a remap in fsp could confuse the TRPx._STA. Ex: Disable TBT controller 0 on b:0 d:7 f:0 Enable TBT controller 1 on b:0 d:7 f:1 The FSP will do the remap and after the remap: TBT controller 1 is on b:0 d:7 f:0 TBT controller 0 is on b:0 d:7 f:1 This is becuase func 0 must exist per pci spec. However, the TRE0-TRE3 will not be remapped so that the ACPI TRPx._STA method could be confused. In such scenario, TRP0._STA will return 0x0, TRP1._STA will return 0xf which is wrong because TBT controller 1 is now at b:0 d:7 f:0 TEST=tested on rex and _TRPx._STA returns correctly. TBT function OK Change-Id: I54f2ea99cd1ec73dd0b71a6ba738aa927b0ae80f Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-07soc/intel/mtl: Fixed TBT PCIe devtree remappingKane Chen
The TBT PCIe devicetree settings are not remapped properly when TBT PCIe port 0 is disabled. This code refer SHA:58bc5d937 to remap the PCIe devtree settings properly in case of TBT PCIe port0 is disabled, TEST=Tested on screebo and found "Remapping PCIe Root Port #2 msg" showed up in coreboot log Change-Id: I7c7549ddf8ccdd67d7af7c69f51a84614cff9a03 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81841 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07device/dram/ddr{3,4}: Rename spd_raw_data for specific DDRElyes Haouas
Rename different spd_raw_data[] for DDR3 and DDR4. This is to solve the conflict when we include both "ddr3.h" and ddr4.h" for example here: src/device/dram/spd.c. Otherwise, it won't compile as DDR3 and DDR4 have different spd_raw_data[] size. Change-Id: I46597fe82790410fbb53d60e04b7fdffb7b0094a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07device/device_util: Add and use is_pci_bridge()Shuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: Ied4921f7dc7e144e580d05d4f2262777aa59d895 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81566 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07soc/intel/xeon_sp/spr: Print return codes for mp_init_with_smmShuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: Iee2234a3055fe8a94ecbfc820e9ff9e981f8dff2 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07soc/intel/xeon_sp/spr: Remove duplicated warningShuo Liu
When microcode is not found, intel_microcode_find() will output warning and skip the update. Remove the duplicated warning in CPU codes. TEST=Build and boot on intel/archercity CRB Change-Id: I0264edc01e90186a7b77d57f9c147d3b73747437 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07soc/intel/xeon_sp/spr: Add comments for get_thread_countShuo Liu
Add comments to clarify the usage of logical core count instead of physical core count. TEST=Build and boot on intel/archercity CRB Change-Id: I2bc94391f060cec9de91183021da03bc5c7438c0 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82097 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07soc/intel/xeon_sp/spr: Remove unused file includes in cpu.cShuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: I17b42331fa9b5f59d1fb1d66b9155c57e258357b Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82191 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06soc/intel/xeon_sp: Add fill_pd_distancesShuo Liu
Update a simple algorithm to cover some basic case for proximity domain distance handling. In the same time, the local variable usage of fill_pds() is optimized. TEST=Build and boot on intel/archercity CRB ACPI SRAT, SLIT and DMAR (Remapping Hardware Static Affinity) are generated correctly for 2S system. Change-Id: I2b666dc2a140d1bb1fdff9bc7b835d5cf5b4bbc5 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Ziang Wang <ziang.wang@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81442 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06common/block/tcss: Add config for PDC<->PMC mux configurationKrishna Prasad Bhat
Introduce a new Kconfig to enable PD controller to PMC mux configuration. Selecting this config enables direct communication from PDC to PMC. TCSS_HAS_USBC_OPS enables USB-C operations via the EC. When SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION is selected, disable TCSS_HAS_USBC_OPS to avoid sending PMC commands from AP/EC. BUG=b:332383540 TEST=USB3 plugged during G3, is detected after system boots from G3. Cq-Depend: chromium:5484387 Cq-Depend: chrome-internal:7106592 Change-Id: Ieeb503393418cdad43384be39ac49c93ba91e4db Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82077 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06soc/intel/xeon_sp/acpi: Refactor Xeon-SP ASL file locationShuo Liu
soc/intel/xeon_sp/acpi/*.asl are actually used only by SKX and CPX platforms and not forward compatible to later SoC generations. Move them to soc/intel/xeon_sp/acpi/gen1/ for clean maintenance. TEST=Build and boot on intel/archercity CRB Change-Id: Ib060b123ab0fd761f00d9a0573e9b73d600ea9ef Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82033 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06block/fast_spi: Use read32p/write32p for SPI RWAshish Kumar Mishra
The current fast_spi code uses memcpy for rw. The SPI flash read/write has 4 byte limit, due to which the current 64 bit memcpy doesn't work. Hence update rw ops to use read32p/write32p. BUG=b:242829490 TEST=Verified MRC cache working on MTL 64-bit, future 64 bit platforms and RPL(brox/skolas) 32-bit platforms. Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-03soc/intel/xeon_sp/spr: Drop unused symbolElyes Haouas
SOC_INTEL_PCIE_64BIT_ALLOC is not used. Change-Id: I1ef52104ef1d883330b800215cb4d0475092d8fe Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-03soc/intel/xeon_sp: Remove unused xeonsp_acpi_create_madt_lapicsShuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: I06e5ff635c37253b1c8f151b62f696ff7e5e22ef Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82110 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02soc/intel/xeon_sp: Use fixed BDF for IBLShuo Liu
Integrated Boot Logic (IBL) codes doesn't support bootloader controlled Primary-to-Sideband Bridge (P2SB) hidden and unhidden. Hence, dynamically read IBL HPET/IOAPIC Bus:Device.Function (BDF) by bootloader is not supported, because when P2SB is hidden the register access is denied. TEST=Build and boot on intel/archercity CRB TEST=Build on intel/avenuecity CRB TEST=Build on intel/beechnutcity CRB Change-Id: I3975cb00e215c4984c63bb8510e8aef7d4cc85a4 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81321 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02soc/intel/xeon_sp: Move VPD based settings to mainboard codesShuo Liu
Configuration variable implementation (VPD, et al) is regarded to be mainboard specific and should not be bounded to SoC codes. This patch moves the VPD based settings (FSP log level, et al) from SoC codes to mainboard codes. TEST=Build and boot on intel/archercity CRB with no significant log differences Change-Id: Iefea72eec6e52f8d1ae2d10e1edbabdebf4dff91 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82090 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-02soc/intel/xeon_sp: Add get_cxl_modeShuo Liu
Configuration variable implementation (VPD, et al) is regarded to be mainboard specific and should not be bounded to SoC codes. Add get_cxl_mode so that SoC codes do not need to get this configuration from VPD any more. TEST=Build and boot on intel/archercity CRB with no significant log differences Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-02soc/intel/xeon_sp: Clean up device enablement configurationFelix Singer
Clean up by using is_devfn_enabled(). Change-Id: I9ea3d8b1b18e84a75a81a7e926d2c638766bb493 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82120 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02soc/intel/cannonlake: Clean up device enablement configurationFelix Singer
Clean up by using is_devfn_enabled(). Change-Id: I9a4984a096e72025e161bf117b70a7c59f2bb094 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82118 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02soc/intel/xeon_sp: Add device to proximity domain map utilsShuo Liu
In NUMA architecture, all devices (cpu, memory and PCI device) belong to specific proximity domain. Add utils to map device instance to their proximity domain. Proximity domain ID is the index assigned at the creation of proximity domains. There is no hard relationship between proximity domain ID and the device identities (e.g. socket ID). Hence we need the map utils to explicitly link them. For now the Sub-NUMA config isn't taken into account. TEST=Build and boot on intel/archercity CRB Change-Id: Icd14a98823491ccfc38473e44a26dddfbbcaa7c0 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Ziang Wang <ziang.wang@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81440 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02soc/intel/xeon_sp: Make NUMA support by defaultShuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: I84f07c16e24e441a885144df8c805f1310acae29 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Ziang Wang <ziang.wang@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81439 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-30soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZEFelix Singer
Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total SPD size of 512 bytes. Set this as the default and remove the setting from mainboard Kconfigs. Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82115 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-29soc/intel/cmn/graphics: Make DDI-A 4 lanes configurableAngel Pons
As described in Intel document 336464 (8th gen S series datasheet volume 1), the CPU's 4 eDP lanes can be bifurcated, so that DDI-A (eDP) ends up with 2 lanes, and DDI-E (DP, typically used for VGA) has the remaining 2 lanes. This lets mainboards provide a VGA output without sacrificing one of the main 4-lane DDIs. Newer platforms seem to be lacking this. However, the way this is structured in coreboot does not allow boards to choose whether bifurcation should be enabled. Most boards in the tree do not use DDI-E (it doesn't exist on mobile platforms), but there are some boards (e.g. hp/280_g2) that use DDI-E and a DP-to-VGA converter chip to provide a VGA output. Replace `SOC_INTEL_CONFIGURE_DDI_A_4_LANES` with two new Kconfig options to allow boards to decide. Use `SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION` to specify whether a platform supports DDI-A bifurcation at all (do nothing otherwise, maintaining the original code's behaviour). If bifurcation is supported, the `SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION` is used to clear or set the `DDI_A_4_LANES` bit in the `DDI_BUF_CTL_A` register. Change-Id: I516538db77509209d371f3f49c920476e06b052f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82113 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-29include/device/pci_ids.h, soc/intel/mtl: add new MTL-P iGPU DIDMichał Kopeć
Found in a Clevo V560TU with Intel Core Ultra 155H Change-Id: I0f10808fd0e2d9c122743615fbce656c6d2447cc Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82071 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-29soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSPShuo Liu
In a server platform many silicon specific register lock operations are by default in FSP space. CHIPSET_LOCKDOWN_FSP provides an option to make sure the codes could be used out-of-box to build products. Change-Id: I8efcc1f27446be8e35f51e2568c4af6f8165486b Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82081 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-23soc/intel/alderlake: Add Twinlake graphics device IDsSowmya V
Add the graphics device IDs for Twinlake platform based on Platform External Design Specification. Document ID: 645548 BUG=b:326901448 TEST=Build tivviks and verify the IGD IDs. Change-Id: Ide008d5c5302bd589784bc917a2610c42a0fdee4 Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82038 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-22drivers/intel/fsp2_0: Introduce fsp print helper macrosAppukuttan V K
This patch introduces fsp print helper macros to print `efi_return_status_t' with the appropriate format. These macros are now used for fsp debug prints with return status efi_return_status_t is defined as UINT64 or UNIT32 based on the selected architecture BUG=b:329034258 TEST=Verified on Meteor Lake board (Rex) Change-Id: If6342c4d40c76b702351070e424797c21138a4a9 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81630 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-22device_util: Handle domain device in dev_get_domainShuo Liu
When the input device pointer pointing to a domain device, dev_get_domain returns the input device itself. TEST=Build and boot on intel/archercity CRB Change-Id: I3a278a8f573de95406ee256fba17767def4ad75d Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-18device/device_util: Rename dev_get_pci_domainShuo Liu
In coreboot, domain indicates hardware units that provide/group resource windows, For Xeon-SP, domains are PCIe compatible and further function in many aspects, e.g. PCIe, CXL, IOAT, UBOX. Rename dev_get_pci_domain to dev_get_domain to align with coreboot concept and distinguish from Xeon-SP concept. TEST=Build and boot on intel/archercity CRB Change-Id: I51b18b30fb41038869ea1384b01091da31a895b9 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-18device/device_util: Use const qualifierPatrick Rudolph
Allows to use the function in more places that expect the struct device to be readonly. TEST=Build and boot on intel/archercity CRB Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81275 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-16lynxpoint/broadwell: Correct L1 exit latency with ASPMAngel Pons
Lynx Point PCH reference code version 1.9.1 programs the larger L1 exit latency when ASPM is enabled. Document 535127 (BDW PCH-LP BS) also does the same. Correct the condition accordingly. On Lynx Point, also remove a now-redundant write to the LCAP register (offset 0x4c). Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57501 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-15soc/intel/xeon_sp/spr: Use official microcodesPatrick Rudolph
Use the official microcode updates from intel-microcode submodule by default. Downstream users can still decide to use their own files. Change-Id: I58121cc2ca7699d3d26581d7d5875ec74deeeb93 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81637 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-04-14soc/intel/broadwell: Add ACPI CIDs for SerialIO devicesAngel Pons
Lynxpoint has them, so add them on Broadwell as well. Change-Id: Iaa3e8044090262a64e58062ec4b116976978ce55 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-04-14lynxpoint/broadwell: Correct PCH-LP PCIe ASPM checkAngel Pons
Lynx Point PCH reference code version 1.9.1 checks bit 29 to detect ASPM on PCH-LP root port #6, not bit 28. Document 535127 (BDW PCH-LP BS) also uses bit 29 for root port #6. Correct the bit used in the check, as well as the surrounding comments. Change-Id: Ie4bd7cbbfc151762f29eab1326567f987b25ab19 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57500 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-30 02:17:19 +0000