diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-06-27 16:24:35 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-07-03 06:13:00 +0000 |
| commit | e27b00a70bf5482a678cb4d467664b3706a73307 (patch) | |
| tree | ff07986042f6b64a0f4128fe13051a9ffac5ad27 /src/soc/intel | |
| parent | 727bc0803722abda1dc1229ac9c7dc4405b5a5c4 (diff) | |
soc/intel/cmn/cse: Modify dependency on CSE EOP configs
Refactor CSE lite End-of-Post (EOP) configs to support
the alternative of sending CSE communication from the payload.
When the SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD config is selected, coreboot
will skip initiating CSE EOP operations and rely on the payload CSE
driver implementation.
The following configs are modified to ensure coreboot skips CSE
communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled:
- SOC_INTEL_CSE_SEND_EOP_EARLY
- SOC_INTEL_CSE_SEND_EOP_LATE
- SOC_INTEL_CSE_SEND_EOP_ASYNC
- SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
BUG=b:305898363
TEST=Able to build google/rex.
Change-Id: Ia6b616163d02be8d637b134fd3728c391fc63c90
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83229
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/cse/Kconfig | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 966726e0f9..d8d2456a1e 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -97,7 +97,7 @@ config SOC_INTEL_STORE_ISH_FW_VERSION config SOC_INTEL_CSE_SEND_EOP_EARLY bool "CSE send EOP early" - depends on SOC_INTEL_COMMON_BLOCK_CSE + depends on SOC_INTEL_COMMON_BLOCK_CSE && !SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD help Use this config to send End Of Post (EOP) earlier through SoC code in order to reduce time required to send EOP and getting CSE response. @@ -106,7 +106,7 @@ config SOC_INTEL_CSE_SEND_EOP_EARLY config SOC_INTEL_CSE_SEND_EOP_LATE bool - depends on SOC_INTEL_COMMON_BLOCK_CSE + depends on SOC_INTEL_COMMON_BLOCK_CSE && !SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD help Use this config to send End Of Post (EOP) late (even after CSE `final` operation) using boot state either `BS_PAYLOAD_BOOT` or `BS_PAYLOAD_LOAD` from common code @@ -119,7 +119,7 @@ config SOC_INTEL_CSE_SEND_EOP_LATE config SOC_INTEL_CSE_SEND_EOP_ASYNC bool - depends on SOC_INTEL_COMMON_BLOCK_CSE + depends on SOC_INTEL_COMMON_BLOCK_CSE && !SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD depends on !SOC_INTEL_CSE_SEND_EOP_LATE depends on !SOC_INTEL_CSE_SEND_EOP_EARLY help @@ -139,10 +139,6 @@ config SOC_INTEL_CSE_SEND_EOP_ASYNC config SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD bool depends on SOC_INTEL_COMMON_BLOCK_CSE - depends on !SOC_INTEL_CSE_SEND_EOP_LATE - depends on !SOC_INTEL_CSE_SEND_EOP_EARLY - depends on !SOC_INTEL_CSE_SEND_EOP_ASYNC - depends on !DISABLE_HECI1_AT_PRE_BOOT help Use this config to specify that the payload will send the End Of Post (EOP) instead of coreboot. |