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authorTony Huang <tony-huang@quanta.corp-partner.google.com>2024-05-20 16:50:56 +0800
committerFelix Held <felix-coreboot@felixheld.de>2024-05-21 13:37:09 +0000
commit62a6188da5080d17afe33a2de9218c7313c2e64b (patch)
tree9da7997b9698d6af80c95bd2f2fad19675e000c8 /src/soc/intel
parent0da12e0f2aee93a1959b6e270fe610074fa03180 (diff)
soc/intel/meteorlake: Add PsysPL2 configuration
psys_pl2_watts is configured in SoC node of devicetree. Value represents Watts. BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot Change-Id: I9c4d62b93fc751db9e0ea04e475acb8861a844f8 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/meteorlake/chip.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index 1b08ccdbd6..0c76b7cda0 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -515,6 +515,9 @@ struct soc_intel_meteorlake_config {
/* Platform Power Pmax in Watts. Zero means automatic. */
uint16_t psys_pmax_watts;
+ /* Platform Power Limit 2 in Watts. */
+ uint16_t psys_pl2_watts;
+
/* Enable or Disable Acoustic Noise Mitigation feature */
uint8_t enable_acoustic_noise_mitigation;
/* Disable Fast Slew Rate for Deep Package C States for VR domains */