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path: root/src/soc/intel/tigerlake/chip.h
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2022-01-14soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a81fd58df468e2711108a3243bf116e02986316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI bit set for any slots of already existing boards, add set the option PcieRpSlotImplemented=1 where appropriate. Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/intel/tigerlake: Hook up DPTF device to devicetreeFelix Singer
Hook up `Device4Enable` FSP setting to devicetree state and drop its redundant devicetree setting `Device4Enable`. The following mainboards enable the DPTF device in the devicetree despite `Device4Enable` is not being set. * google/deltaur Thus, set it to off to keep the current state unchanged. Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/intel/tigerlake: Drop unused SataEnable settingFelix Singer
`SataEnable` is set by some boards, but it doesn't have any effect since its related FSP option is hooked up to the devicetree state. Thus, drop it. Change-Id: Id645bfcade7ca1d495fb8df538113b3d10392a82 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-09soc/intel/tigerlake: Hook up SMBus device to devicetreeFelix Singer
Hook up `SmbusEnable` FSP setting to devicetree state and drop its redundant devicetree setting `SmbusEnable`. The following mainboards enable the SMBus device in the devicetree despite `SmbusEnable` is not being set. * google/deltaur * starlabs/laptop Thus, set it to off to keep the current state unchanged. Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-12soc/intel: replace dt option PmTimerDisabled by KconfigMichael Niewöhner
Replace the dt option `PmTimerDisabled` with use of the Kconfig option `USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer. A default value representing the prior devicetree value was added to the boards system76/{lemp10,galp5,darp7}, so this change will not alter behaviour. Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-07soc/intel/tigerlake: Hook up GMA ACPI brightness controlsTim Crawford
Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Tested by adding gfx register on system76/gaze16 and booting Windows. Display settings has a brightness setting, and can change the brightness level. Change-Id: Id8b14c0b4a7a681dc6cb95778c12a006a7e31373 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-01soc/tigerlake: Make IO decode / enable register configurableSean Rhodes
This allows the one 32bit register to be configured in the devicetree in the same way that Skylake can be. i.e. register "lpc_ioe". Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib1a7f2707e565a5651ebe438320de9597f5742c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-24soc/intel/tigerlake: Add TGL-H power limitsJeremy Soller
Convert the power limit defines to an enum and add TGL-H entries. Change-Id: I6fa7c7338b3157b29ff72769238597e3c528aedb Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OCNick Vaccaro
We need to change OC pin for type C USB3 ports and it depends on the board design. Allowing it to be filled by devicetree will make it easier to change the mapping based on the board design. BUG=b:184660529 TEST="emerge-volteer coreboot" compiles without error. Change-Id: I5058a18b1f4d11701cebbba85734fbc279539e52 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias padsTim Wawrzynczak
TGL boards using the Type-C subsystem for USB Type-C ports without a retimer attached may require a DC bias on the aux lines for certain modes to work. This patch adds native coreboot support for programming the IOM to handle this DC bias via a simple devicetree setting. Previously a UPD was required to tell the FSP which GPIOs were used for the pullup and pulldown biases, but the API for this UPD was effectively undocumented. BUG=b:174116646 TEST=Verified on volteer2 that a Type-C flash drive is enumerated succesfully on all ports. Verified all major power flows (boot, reboot, powerdown and S0ix/suspend) still work as expected. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-21soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRCRizwan Qureshi
CONFIG_MAX_PCIE_CLOCKS renamed to MAX_PCIE_CLOCK_SRC to make it clear that this config is for the number of PCIe Clock sources available which is different from PCIe clock reqs. This is more relevant in alderlake, as the number clock source and clock reqs differ. However since this is a better name, renaming it throughout the soc/intel tree. Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I747c94331b68c4ec0b6b5a04149856a4bb384829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52194 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06intel/tigerlake: Add Acoustic featuresShaunak Saha
On VCCin there was an oscillation which occurred just as the kernel started (kernel starting... message). On some devices, this behavior seems even worse. In previous platforms VCCin toggled for a few ms and then was stable. For volteer, this happens at the same point in time for around 40ms. However, it starts oscillating again later in the boot sequence. Once at the root shell, it seems to oscillate indefinitely at around 100-200Hz (very variable though). To fix this we need to control the deep C-state voltage slew rate.We have options for controlling the deep C-state voltage slew rate through FSP UPDs. This patch expose the following FSP UPD interface into coreboot: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRate We are setting SlowSlewRate for all volteer boards to 2 which is Fast/8. TGL has a single VR domain(Vccin). Hence, the chip config is updated to allow mainboards to set a single value instead of an array and FSP UPDs are accordingly set. BUG=b:153015585 BRANCH=firmware-volteer-13672.B TEST= Measure the change in noise level by changing the UPD values. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-19soc/intel/tgl: Add configurable value for PmcUsb2PhySusPgEnableDerek Huang
PmcUsb2PhySusPgEnable is enabled by default. Expose devicetree parameter to disable Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: Ibd54a10c57d39bb8762b705ef0d6ff4cd47f0d89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-03-15soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entryCliff Huang
FSP has added the Cnvi BT Core enabling in addition to the existing CnviMode. This change adds the flag at the soc config side (i.e. soc_intel_tigerlake_config for devicetree). Also, there is no longer PCI host interface for BT. Therefore, BT core should not use the pci port status to turn on/off. TEST: BT enumeration is checked using 'lsusb -d 8087:0026' from OS to make sure BT is turned on. Change-Id: I71c512fe884060e23ee26e7334c575c4c517b78d Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03soc/intel: Retype `CnviBtAudioOffload` devicetree optionAngel Pons
The `FORCE_ENABLE` and `FORCE_DISABLE` names do not match what FSP UPDs say, and can be confused with the `PchHdaTestPowerClockGating` UPD. Replace the enum with a bool, and drop the confusing names. Note that the enum for Ice Lake was incorrect, but no mainboards used the option. Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51154 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard designShreesh Chhabbi
This change uses the following information to determine the appropriate S0ix states to enable as per PDG document: 607872 for TGL UP3 UP Rev2p2 (section 10.13): 1. SoC - UP3 v/s UP4 2. H/W design - external phy gating, external clk gating, external bypass 3. Devices enabled at runtime - CNVi, ISH In some cases, it is recommended to use a shallower state for S0ix even if the higher state can be achieved (e.g. with external gating not enabled). This recommendation is because the shallower state is determined to provide better power savings as per the above document. Deepest state expected on tigerlake up3 based platforms is S0i3.2. BUG=b:177821896 TEST=Build coreboot for volteer. Verify that deepest S0ix substate that is enabled is S0i3.1 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49766 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03soc/intel/tgl: Add configurable value for ConfigTdpLevelDerek Huang
According to Tigerlake TDP specifications (doc #575683, table 4-2), TGL supports different TDP levels depends on CPU segement/package, IA Cores and graphics configuration. For example, UP3 4-Core GT2 suppots base TDP=28W, Configurable TDP-Down_1=15W and Configurable TDP-Down_2=12W. This configurable value can be used to select suitable TDP level Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5 Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-01-18soc/intel/common: Move L1_substates_control to pcie_rp.hEric Lai
L1_substates_control is common define. Move out of soc level. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I54574b606985e82d00beb1a61cce3097580366a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-14soc/intel/tgl: Add configurable value for UsbTcPortEnBrandon Breitenstein
As a requirement of TCSS this setting needs to be correctly set to determine what Type-C ports are enabled on the platform. Without this value correctly set there can be adverse effects on the other TCSS specific values. BUG=b:159151238 BRANCH=firmware-volteer-13672.B TEST=Built image for Voxel and verified that S0ix cycles no longer fail when the IomPortPad is set to 0 Change-Id: I6c5260cda71041439fe89d15bd3cafd4052ef1e7 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-12-30soc/intel: hook up new gpio device in the soc chipsMichael Niewöhner
This change adds the required gpio operations struct to soc/common gpio code and hooks them up in all socs currently using the gpio block code, except DNV-NS, which is handled in a separate change. Also, add the gpio device to existing chipset devicetrees. Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with CB:48711 and OCP DeltaLake with CB:48672. Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48583 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/tigerlake: Drop unreferenced devicetree settingsAngel Pons
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: I5f5da8dfcec7dd35981611830b555cab5d6af3e3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48572 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20soc/intel/tigerlake: Expose UPD to enable Precision Time MeasurementDuncan Laurie
Expose a config option that allows enabling the FSP UPD which controls Precision Time Measurement for a particular PCIe root port. This UPD is enabled by default in FSP but interferes with achieving deeper S0ix substates so in order to prevent it from needing to be explicitly disabled for every root port this change makes disabling it the default and allows it to be enabled if needed. BUG=b:160996445 TEST=boot on volteer with PTM disabled by default for all root ports and ensure S0i3.2 substate can be achieved. Change-Id: Icb51b256eb581d942b2d30fcabfae52fa90e48d4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46856 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09soc/intel/*/chip: Remove unused devicetree entryPatrick Rudolph
InternalGfx isn't used so drop it. Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-10-23soc/intel/tigerlake: Add Acoustic featuresShaunak Saha
Expose the following FSP UPD interface into coreboot: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRateFor BUG=b:153015585 BRANCH=none TEST= Measure the change in noise level by changing the UPD values. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: I1924a3bac8beb16a9d841891696f9a3dea0d425f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-23soc/intel/tigerlake: Configure FSP UPDs for minimum assertion widthsJamie Ryu
Configure FSP UPDs for the chipset minimum assertion widths and power cycle duration per mainboard variants. * PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy * PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy * PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy * PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy * PchPmPwrCycDur: PCH PM Reset Power Cycle Duration * Check to avoid violating the PCH EDS recommendation for the PchPmPwrCycDur setting. BUG=b:159108661 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I8180d95a2185c3786334e10613f47e77b7bc9d5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44557 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14soc/intel/{cnl,icl,jsl,tgl}: Clean up chip.hSubrata Banik
Removed unused header files in chip.h Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Idb9b1ed23df3dbb9dad4d36651064c21a4d913fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/45322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-08-17soc/intel/tigerlake: Allow fine grained control of S0iX statesJes Klinke
Expose devicetree parameter to enable/disable each individual substate. See https://review.coreboot.org/c/coreboot/+/43741 for context. TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x BUG=b:154333137 Change-Id: I8a0cf820e20961486813067c6945fe07bc4899f7 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/44355 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29soc/intel/tigerlake: Configure TCSS D3Hot and D3ColdJohn Zhao
Update configuration for both of TCSS D3Hot and D3Cold. It is expected D3Hot is enabled for all platforms. Because there are known limitations for D3Cold enabling on pre-QS platform, this change reads cpu id and disables D3Cold for pre-QS platform. For QS platform, D3Cold is configured to be enabled. BUG=None TEST=Verified D3Hot is enabled, D3Cold is disabled for pre-QS (cpu:806c0) and enabled for QS (cpu:0x806c1). Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I534ddfefcd182f5b35aa5e8b461f0920d375a66d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43980 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26src/soc/intel: Add include <types.h>Elyes HAOUAS
BIT(x) needs <types.h>. Change-Id: I674e3e423e06ee869366ebbd7c9d4248a2f3d9d9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKUSumeet R Pawnikar
Set power limits in devicetree for Tiger Lake Y-SKU based volteer variant boards. BUG=b:152639350 BRANCH=None TEST=Built and tested power limits on volteer variant board. Change-Id: If4f1226473b48365e5962df9fff29910c99007fc Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43607 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15soc/intel/tigerlake: Hook up SATA Port Enable DITO UPDsShaunak Saha
SataPortsEnableDitoConfig Enable DEVSLP Idle Timeout settings DmVal and DitoVal. SataPortsDmVal and SataPortsDitoVal helps to determine when to enter Device Sleep. Device Sleep enables the host bus adapter (HBA) to assert the DEVSLP signal as soon as there are no commands outstanding to the device and the port specific Device Sleep idle timer has expired. Device Sleep Idle Timeout values (PxDEVSLP.DITO and PxDEVSLP.DM) are port specific timeout values used by the HBA for determining when to assert the DEVSLP signal. They provides a mechanism for the HBA to apply a programmable amount of hysteresis so as to prevent the HBA from asserting the DEVSLP signal too quickly which may result in undesirable latencies. This patch is created based on Intel Tiger Lake Processor PCH Datasheet with Document number:575857 and Chapter number:12. * PxDEVSLP.DM -> SataPortsDmVal: Enable SATA Port DmVal DITO multiplier. Default is 15. * PxDEVSLP.DITO -> SataPortsDitoVal: Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625ms. BUG=b:151163106 BRANCH=None TEST=Build and boot volteer and TGL RVP. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: I6a824524738a9e0609f54bea9d892b4a42a1d3db Reviewed-on: https://review.coreboot.org/c/coreboot/+/42214 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09mainboard/intel/tglrvp: Remove unused PrmrrSize chip configSubrata Banik
Refer to commit 7736bfc TEST=Able to build and boot TGLRVP. Change-Id: Ie9a97cee7d7793077167db3a642dcbca45b09427 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43139 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/intel/tigerlake: Add CpuReplacementCheck to chip optionsJamie Ryu
Add CpuReplacementCheck to chip options to control UPD FSPM SkipCpuReplacementCheck from devicetree. This UPD allows platforms with soldered down SoC to skip CPU replacement check to avoid a forced MRC traning. TEST=boot and verified with volteer Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42788 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22soc/intel/tigerlake: Add CmdMirror option in chip.hDavid Wu
Provide CmdMirror option in chip.h so that it can control CmdMirror FSP UPD via dev tree. BUG=b:156435028 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Idae9fa439f077f8f3fb16fe74c2f263c008cd5f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42276 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/volteer: Override power limits with SKU-specific limitsTim Wawrzynczak
Using guidance from Intel, a new set of power limits (PL1, PL2 & PL4) are available for TGL-U. They are dependent upon the SKU of the CPU that the mainboard is running on. Volteer is updated here to use these new limits. To accomplish this, the SoC chip config's power_limits_config member was expanded to an array, which can be indexed by POWER_LIMITS_*_CORE macros. Just before power limits are applied, the correct set of them is chosen from the array based on System Agent PCI ID. Therefore, a TGL board should have two sets of power limits available in the devicetree. BUG=b:152639350 TEST=On a Volteer SKU4 (4-core), verified the following console output: CPU PL1 = 15 Watts CPU PL2 = 60 Watts CPU PL4 = 105 Watts Change-Id: I18a66fc3aacbb3ab594b2e3d6e2a4ad84c10d8f0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-06-17soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPDWonkyu Kim
This patch adds support for enabling/disabling PCIe hot-plug via a chip config option PcieRpHotPlug, which is copied to the corresponding FSP-S UPD. BUG=b:156879564 BRANCH=none TEST=Boot Volteer/RVP with FSP log and check hotplug enabled/disabled Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I4c0187644b6ca9735f1b159e110e3466af14ff71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41794 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-12soc/intel/tigerlake: Add devicetree support to change PCH VR settingsVenkata Krishna Nimmagadda
For Tiger Lake platforms, this patch set provides a way to override PCH external VR settings and ext rail voltage/current through devicetree. This enables setting of optimal settings for FIVRs for a particular PCH type. BUG=None BRANCH=None TEST=Build and boot volteer. Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Ic55472d392f27d153656afbe8692be7e243bb374 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41424 Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMsJohn Zhao
The Connect Topology Command(CNTP) is sent with default timeout value (0x1388) along with FW CM. The CNTP is supposed to be skipped while using SW CM. While transition from FW CM to SW CM, the default timeout value could cause boot time delay up to ~10 seconds. Set this FSPS UPD ITbtConnectTopologyTimeoutInMs to be 0 in order to avoid the 10 seconds delay. Future FSP release will evaluate this ITbtConnectTopologyTimeoutInMs value. While FSP finds this UPD value being 0, FSP will skip sending CNTP. BUG=b:155893566 TEST=Built image with SW CM Thunderbolt firmware and verified no outstanding delay time while using FSP v3197 during boot to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I47e3519fd818cb56e6abd16464d8370ffddabc5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42056 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-30soc/intel/tigerlake: Configure TcssDma0En and TcssDma1EnJohn Zhao
Determine the TcssDma0 and TcssDma1 enabling based on TBT DMA controllers setting. BUG=:b:146624360 TEST=Booted on Volteer and verified TcssDma0 and TcssDma1 enabling. lspci shows TcssDma0(0d.2) and TcssDma1(0d.3). Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I61ac4131481374e9a2a34d1a30f822046c3897fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/41812 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26soc/intel/tigerlake: Remove MIPI clock setting from devicetreeSrinidhi N Kaushik
In Tiger Lake we have support for enabling MIPI clocks at runtime in ACPI. Hence remove setting pch_islclk from devcietree and chip.h. Also update functions which reference pch_isclk. BUG=b:148884060 Branch=None Test=build and boot volteer and verify camera functionality Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I6b3399172c43b4afa4267873ddd8ccf8d417ca16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41570 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26soc/intel/tigerlake: Delete unused configurationWonkyu Kim
Delete below configuration - Heci3Enabled: deprecated, see https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h#n442 - PchIshEnable: don't need as it's handled by devicetree dev on/off, see https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/romstage/fsp_params.c#n87 BUG:b:151166877 BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: If96cc7db7118dd6c2ac02aab3bb0c96763ffc722 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-26soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnableJohn Zhao
This adds FSP UPD D3HotEnable and D3ColdEnable for configuration. D3Hot low power mode support is for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers. D3Cold is lower mode for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold transition. BUG=:b:146624360 TEST=Built and booted on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I6782cde6a1bfe13f46e75db8c85537c6d62f5d41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-20tigerlake: update processor power limits configurationSumeet R Pawnikar
Update processor power limit configuration parameters based on common code base support for Intel Tigerlake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on volteer system Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39345 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfgBrandon Breitenstein
In order for the SOC to be able to control the Aux line orientation for Type-C ports that do not have a retimer, the IomTypeCPortPadCfg UPD needs to be configurable through devicetree to correctly set the GPIO pins that the SOC should use to flip orientation. BUG=b:145220205 BRANCH=NONE TEST=booted Volteer proto 2 and verified that the AUX channels flip when the cable is flipped Change-Id: I2e48adb624c7922170eafb8dfcaed680f008936e Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40244 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1EnJohn Zhao
This adds FSP UPD TcssDma0En and TcssDma1En for configuration. BUG=:b:146624360 TEST=Built and booted on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I04af970f74ab9dfe84f9c0c09ec2098e0093fa57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-05-18soc/intel/tigerlake: Add PchHdaIDispCodecDisconnect overrideEric Lai
This is a missing config override in fspm_upd. iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. BUG=b:156447983 TEST=None Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifbbc22d14e06713009c550cbe8a7292de64e1fdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/41394 Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12soc/intel/tigerlake: Control SATA and DMI power optimizationShaunak Saha
FSP provides the UPD's for SATA and DMI power optimization. In this patch we are adding the soc's config support to set those power optimization bits in FSP. By default those optimizations are enabled. To disable those we need to set the DmiPwrOptimizeDisable and SataPwrOptimizeDisable to 1 in devicetree. BUG=b:151162424 BRANCH=None TEST=Build and boot volteer and TGL RVP. Change-Id: Iefc5e7e48d69dccae43dc595dff2f824e53f5749 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better ↵Subrata Banik
understanding BIT 1 -> DEBUG_INTERFACE_UART_8250IO BIT 4 -> DEBUG_INTERFACE_LPSS_SERIAL_IO Change-Id: I566b9dc82b2289af42e58705ebeee51179886f1f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-01soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetreeMeera Ravindranath
This CL adds support to fill PcieRpClkReqDetect UPD from devicetree. Filling this UPD will allow FSP to enable proper clksrc gpio configuration. BUG=None BRANCH=None TEST=Build and boot tglrvp. Change-Id: Iad0ba94fea019623a5b98fff0cb4a2cd1d2a7bd7 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-04-20soc/intel/tigerlake: Update iDisp Link UPD settingsSrinidhi N Kaushik
Remove explicit setting of iDisp Link parameters. These settings are related to configuration for the link between HD-Audio controller and Display unit for purposes of HDMI/DP Audio playback. During PO, observed that without setting these params display part was not binding. With the latest code verified that we dont need to explicitly set these parameters anymore. HDMI/DP audio playback works fine with default settings. BUG=b:151451125 BRANCH:none TEST= build and boot volteer/ripto and verify HDMI/DP audio playback Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40263 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jairaj Arava <jairaj.arava@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-17soc/intel/tigerlake: Remove eMMC/SD supportDuncan Laurie
Tigerlake platform does not have built in eMMC/SD support so all this code is unused and can be removed. Change-Id: I70ff983d175375171d5a649378f32f1062c0876d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40372 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14soc/intel/tigerlake: Configure RP settingWonkyu Kim
Add LTR and AER configuration to the root ports config. BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I668f2e5fea15019a9e5ae06fb4d55fa2aea69e8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/40262 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06soc/intel/tigerlake: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I482715c166ccf5d2f3cc25118d25b07dbfd6650a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-03-30soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3Brandon Breitenstein
FSP UPD TcssAuxOri is used for setting the IOM_TYPEC_SW_CONFIGURATION_3. Configure TcssAuxOri to retimer enabled on the port 2 Type-C port. This setting informs the SoC that a retimer is taking care of SBU orientation therefore it does not need to do any flipping. The IOM_TYPEC_SW_CONFIGURATION_3 is a bitfield that controls the aux orientation settings for the Type-C ports. The TGL EDS describes this setting and what each bit represents. Reference section 3.6.5 in TGL EDS #575681 BUG=b:145943811 BRANCH=none TEST=Boot to OS and check Type-C port1 Display on volteer, Connecting Type-C display should work regardless of Type-C cable orientation. Change-Id: Iae356113cbdc72983f800060b1ebebe3c66b9daf Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39459 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25soc/intel/tigerlake: Configure HyperthreadingWonkyu Kim
Configure Hyperthreading based on devicetree BUG=none TEST= Build and boot with FSP log and check Hyperthread setting Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Idc94e6b8ecd59a43be60bf60dc7dd0811ac0350b Reviewed-on: https://review.coreboot.org/c/coreboot/+/39683 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-15soc/intel/tigerlake: Enable CNVi through dev_enabledSrinidhi N Kaushik
Check for dev enabled status for CNVi and update the UPD accordingly. BUG=none BRANCH=none TEST=Build and boot tglrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I15a03cc70f12e094badf942dd81f22bd09531051 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-03-15soc/intel/tigerlake: Update Cpu Ratio settingsSrinidhi N Kaushik
Add config to override CpuRatio or setting CpuRatio to allowed maximum processor non-turbo ratio. BUG=151175469 BRANCH=none TEST=Build and boot tglrvp and observe there is no extra reset in meminit. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I2fa883b443d0a4c77d62275faeacd1ed2c67a97c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39493 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-12soc/intel/tigerlake: Configure L1Substates for PCH Root portsWonkyu Kim
Set value for PcieRpL1Substates according to devicetree. Chip config parameter PcieRpL1Substates uses (UPD value + 1) because UPD value of 0 for PcieRpL1Substates means disabled for FSP. In order to ensure that mainboard setting does not disable L1 substates incorrectly, chip config parameter values are offset by 1 with 0 meaning use FSP UPD default. get_l1_substate_control() ensures that the right UPD value is set in fsp_params. Chip config parameter values 0: Use FSP UPD default 1: Disable L1 substates 2: Use L1.1 3: Use L1.2 (FSP UPD default) BUG=none BRANCH=none TEST=Boot up and check FSP log for PCIe config for this values Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I66743a29ad182bd49b501ae73b79270a9eb88450 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39412 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-11soc/intel/tigerlake: Correct FSP log interfaceRonak Kanabar
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART Add check for DEBUG_INTERFACE_TRACEHUB selection and set "PcdDebugInterfaceFlags" UPD accordingly. BUG=None TEST=boot jslrvp board with Debug FSP and check FSP UART log Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-03-10soc/intel/tigerlake: Enable Hybrid storage modeWonkyu Kim
To use Optane memory, we need to set 2x2 PCIe lane mode while we need to set 1x4 PCIe lane mode for NVMe. The mode can be selected using the FIT tool at build time. By enabling hybrid storage mode in FSP, FSP will set 2x2 PCIe lane mode if Optane memory is detected and the mode is not 2x2 and set 1x4 PCIe lane mode if Optane memory is not detected and the mode is not 1x4 during boot up. The mode is saved in SPI NOR for next boot. BUG=b:148604250 BRANCH=none TEST=Build and test booting TGLRVP from NVMe and Optane Check PCIe lane configuration. Show all the NVMe devices lspci -d ::0108 Show all the NVMe devices and be really verbose lspci -vvvd ::0108 Print PCIe lane capabilities and configurations for all the NVMe devices. lspci -vvvd ::0108 | grep -e x[124] Print all the PCIe information of the device ae:00.0 lspci -vvvs ae: Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39232 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06soc/intel/tigerlake: Enable CNVi ModeSrinidhi N Kaushik
Add configs to enable CNVi mode and CNViBtCore. BUG=none BRANCH=none TEST=Build and boot tglrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ic372348a1409b2594a85b71b2fc742be96b84b87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39317 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-04src: capitalize 'PCIe'Elyes HAOUAS
Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-03soc/intel/tigerlake: Add Jasper lake GPIO supportRonak Kanabar
Add gpio definition for Jasper Lake gpio controller. Also created a separate file for JSL and TGL gpio keeping common asl file. gpio_soc_defs.h must pass correct information/macro values to asl file for code to work. GPIO controller includes 4 gpio community and 10 groups. Patch adds definition for all gpio within community and groups Updated IRQ mapping for all gpios TEST=Check if jslrvp and tglrvp code is compiling Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-03-01soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by KconfigSubrata Banik
This change is mainly to control PlatformDebugConsent FSP UPD. PlatformDebugConsent is enabled if SOC_INTEL_<SOC>LAKE_DEBUG_CONSENT != 0. PlatformDebugConsent in FspmUpd.h has the details. TEST=Able to connect ITP/DCI with target system. Change-Id: I39fe84025cb2bff186d61b2fcad531db52e2b440 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-02-27soc/intel/tigerlake: Update FSP params for Jasper LakeMaulik V Vaghela
Update FSP parameters for various configurations like: - graphics - USB - PCIe root ports - SD card - eMMC - Audio - Basic UART configuration These are the initial settings for JSL. This patch also corrects the debug_interface_flag definitions. TEST=Build dedede board Change-Id: Ia8e88f92989fe40d7bd1c28947e005cc0d862fcb Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-02-17soc/intel/tigerlake: Enable Audio on TGLSrinidhi N Kaushik
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue. BUG=b:147436144 BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db Reviewed-on: https://review.coreboot.org/c/coreboot/+/38147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-02-01soc/intel/tigerlake: Configure TCSS xHCI and xDCIWonkyu Kim
Configure xHCI, xDCI according to board design BUG=none BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-28soc/intel/tigerlake: Enable DP ports according to board designWonkyu Kim
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ia6e9271a11a1f9e6f98923772219ccc1e7daecda Reviewed-on: https://review.coreboot.org/c/coreboot/+/38528 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/tigerlake: Update chip filesRavi Sarawadi
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure Reference PCH EDS#576591 vol1 rev1.2 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-12soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.hFurquan Shaikh
gpe0_en_* seem to have been copied over from previous generations but recent SoCs don't use it. This change gets rid of these unused members. Change-Id: I165e66aeefde4efea4484f588c774795987ca461 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-09soc/intel/tigerlake: Do initial SoC commit till ramstageSubrata Banik
Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 5.c Remove dGPU over PCIE enable Kconfig option 6. Add CPU/PCH/SA EDS document number and chapter number 7. Remove unnecessary headers from .c files based on review Tiger Lake specific changes will follow in subsequent patches. 1. Include GPIO controller delta over ICL 2. FSP-S related UPD overrides as applicable Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36087 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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