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authorWonkyu Kim <wonkyu.kim@intel.com>2020-01-28 22:06:37 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-02-01 19:55:03 +0000
commit1ab6f0c176c1aa6947bf0d3fbe0a213f316e9c67 (patch)
tree79b610c87ced9a8f46b705dab031521cdef2e3df /src/soc/intel/tigerlake/chip.h
parente7601b5d6c6c3a0fdf0d779cfe12b9a381f0fba4 (diff)
soc/intel/tigerlake: Configure TCSS xHCI and xDCI
Configure xHCI, xDCI according to board design BUG=none BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
-rw-r--r--src/soc/intel/tigerlake/chip.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 3f980d1552..4f57b0e07a 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
+ * Copyright (C) 2019-2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -218,6 +218,10 @@ struct soc_intel_tigerlake_config {
FORCE_ENABLE,
} CnviBtAudioOffload;
+ /* Tcss */
+ uint8_t TcssXhciEn;
+ uint8_t TcssXdciEn;
+
/*
* Override GPIO PM configuration:
* 0: Use FSP default GPIO PM program,