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authorTim Wawrzynczak <twawrzynczak@chromium.org>2020-06-16 10:50:47 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-06-22 12:24:11 +0000
commit2dcca0f924f9c4aa230c27808f772623b4cea061 (patch)
tree21a20bd5734cfb7ea508ebdc567b5016fee6d260 /src/soc/intel/tigerlake/chip.h
parenta31a76976097c7d7b28b7cf0f67cb2d6c66ded48 (diff)
mb/google/volteer: Override power limits with SKU-specific limits
Using guidance from Intel, a new set of power limits (PL1, PL2 & PL4) are available for TGL-U. They are dependent upon the SKU of the CPU that the mainboard is running on. Volteer is updated here to use these new limits. To accomplish this, the SoC chip config's power_limits_config member was expanded to an array, which can be indexed by POWER_LIMITS_*_CORE macros. Just before power limits are applied, the correct set of them is chosen from the array based on System Agent PCI ID. Therefore, a TGL board should have two sets of power limits available in the devicetree. BUG=b:152639350 TEST=On a Volteer SKU4 (4-core), verified the following console output: CPU PL1 = 15 Watts CPU PL2 = 60 Watts CPU PL4 = 105 Watts Change-Id: I18a66fc3aacbb3ab594b2e3d6e2a4ad84c10d8f0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
-rw-r--r--src/soc/intel/tigerlake/chip.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 30377aaf79..8b1fe2d03f 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -22,6 +22,11 @@
#define MAX_HD_AUDIO_SNDW_LINKS 4
#define MAX_HD_AUDIO_SSP_LINKS 6
+/* The first two are for TGL-U */
+#define POWER_LIMITS_U_4_CORE 0
+#define POWER_LIMITS_U_2_CORE 1
+#define POWER_LIMITS_MAX 2
+
/*
* Enable External V1P05 Rail in: BIT0:S0i1/S0i2,
* BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5
@@ -55,7 +60,7 @@ struct soc_intel_tigerlake_config {
struct soc_intel_common_config common_soc_config;
/* Common struct containing power limits configuration information */
- struct soc_power_limits_config power_limits_config;
+ struct soc_power_limits_config power_limits_config[POWER_LIMITS_MAX];
/* Gpio group routed to each dword of the GPE0 block. Values are
* of the form PMC_GPP_[A:U] or GPD. */