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authorWonkyu Kim <wonkyu.kim@intel.com>2020-03-09 13:34:38 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-03-12 07:40:11 +0000
commit84b4882b99e92665ea6db933f8180b489b1759b4 (patch)
tree35f78e23c427398bc39af01f767ec41070affb8e /src/soc/intel/tigerlake/chip.h
parent9a2922871d365dbaa373e155c3a72bae4a9d8204 (diff)
soc/intel/tigerlake: Configure L1Substates for PCH Root ports
Set value for PcieRpL1Substates according to devicetree. Chip config parameter PcieRpL1Substates uses (UPD value + 1) because UPD value of 0 for PcieRpL1Substates means disabled for FSP. In order to ensure that mainboard setting does not disable L1 substates incorrectly, chip config parameter values are offset by 1 with 0 meaning use FSP UPD default. get_l1_substate_control() ensures that the right UPD value is set in fsp_params. Chip config parameter values 0: Use FSP UPD default 1: Disable L1 substates 2: Use L1.1 3: Use L1.2 (FSP UPD default) BUG=none BRANCH=none TEST=Boot up and check FSP log for PCIe config for this values Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I66743a29ad182bd49b501ae73b79270a9eb88450 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39412 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
-rw-r--r--src/soc/intel/tigerlake/chip.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index d23148aac8..9fc70f8a46 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -122,6 +122,14 @@ struct soc_intel_tigerlake_config {
* clksrc. */
uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
+ /* PCIe RP L1 substate */
+ enum L1_substates_control {
+ L1_SS_FSP_DEFAULT,
+ L1_SS_DISABLED,
+ L1_SS_L1_1,
+ L1_SS_L1_2,
+ } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
+
/* SMBus */
uint8_t SmbusEnable;