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authorDavid Wu <david_wu@quanta.corp-partner.google.com>2020-06-11 14:46:24 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-06-22 12:28:23 +0000
commit63ce260a3ea8da00973d48af7c04a215e8163985 (patch)
treec43c94391dd8883ac83f64c06c02a7ec5197cb79 /src/soc/intel/tigerlake/chip.h
parentfeecdc2c0bac3dd4ebc1e24b047b9374a4d9d25d (diff)
soc/intel/tigerlake: Add CmdMirror option in chip.h
Provide CmdMirror option in chip.h so that it can control CmdMirror FSP UPD via dev tree. BUG=b:156435028 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Idae9fa439f077f8f3fb16fe74c2f263c008cd5f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42276 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
-rw-r--r--src/soc/intel/tigerlake/chip.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 8b1fe2d03f..c72698f3d6 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -115,6 +115,9 @@ struct soc_intel_tigerlake_config {
/* Rank Margin Tool. 1:Enable, 0:Disable */
uint8_t RMT;
+ /* Command Pins Mirrored */
+ uint32_t CmdMirror;
+
/* USB related */
struct usb2_port_config usb2_ports[16];
struct usb3_port_config usb3_ports[10];