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2022-06-22soc/intel/alderlake: add GPIO definitions for PCH-SMichał Kopeć
Add GPIO definitions for ADL-S, similarly to how TGL/TGL-H handles the split. Based on: - Intel PCH-S EDS Vol2 (#621483) - Alderlake-S FSP - slimbootloader sources - Linux alderlake-pinctrl driver Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-22soc/intel/alderlake: Remove menu option for MAX_PCIE_CLOCK_SRCCliff Huang
MAX_PCIE_CLOCK_SRC is not an user-configurable option. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: Ia49f6e236e8853c377e9096500d96f21dbdc9b8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65298 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/intel/alderlake: Allow possible options for MP InitSubrata Banik
This patch creates choice that lists all possible options to perform MP Init as below: 1. USE_FSP_MP_INIT: Allow coreboot to bring APs from reset and FSP runs feature programming based and selects MP_SERVICES_PPI_V2 config. 2. USE_COREBOOT_MP_INIT: Allow coreboot to perform MP Init (both AP init and feature programming) using native implementation. Additionally, selects required RELOAD_MICROCODE_PATCH when coreboot is expected to run MP Init. Refactor SoC code to allow required FSP UPD override based on selected MP Init option. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I20adc1935890c4c6bcd11fd086838f15d0723932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64977 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20soc/intel/alderlake/chip.c: Add missing ADL-S USB ports ACPI namesMichał Żygowski
ADL-S has more USB ports than mobile chipsets. Add missing ACPI names. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ice5f7784f9de0364681be00fc5cc445caf9d1b3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63655 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-18soc/intel/alderlake: Skip PCIe source clock assignment if incorrectCliff Huang
When an enabled root port without pcie_rp clock being specified, the empty structure provides invalid info, which indicates '0' is the clock source and request. If a root port does not use clock source, it should still need to provide pcie_rp clock structure with flags set to PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it is considered that pcie_rp clock structure is not provided for that root port. Add check and skip for enabled root port that does not have clock structure. In addition, a root port can not use a free running clock or clock set to LAN. Note that ClockUsage is either free running clock, LAN clock, or the root port number which consumes the clock. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I17d52374c84ec0abf888efa0fa2077a6eaf70f6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-17soc/intel/{alderlake, common}: Rename the pre_mem_ft structureSridhar Siricilla
The patch renames identifiers (macros, function and structure names) in the basecode/debug/debug_feature.c to generic names so that they can be used to control the features which may have to be controlled either during pre and post memory. Currently, the naming of identifiers indicate that it meant to control the features which can be controlled during only pre-memory phase. TEST=Build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I53ceb25454027ab8a5c59400402beb6cc42884c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-17soc/intel/alderlake/report_platform.c: Add ADL-S identificationMichał Żygowski
Based on DOC #619501, #619362 and #618427 TEST=Boot MSI PRO Z690-A DDR4 WIFI and see the silicon info is reported as ADL-S. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8051113515ef63fc4687f53d25140a3f55aadb6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-16soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-SMichał Żygowski
Alder Lake-S CPUs do not have TCSS and USB4 devices. Unselect them. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ifc643d440107754dfe1a0844964f70de670cb1f1 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-16soc/intel/alderlake/fsp_params.c: Add VccIn Aux Imon IccMax for ADL-SMichał Żygowski
Based on DOC #619501. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia95404e717787edbdb67c9e584e749526b973427 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15soc/intel/adl: Add missing claimed memory regionsEran Mitrani
The Alder Lake chipset has several more reserved memory regions that are unavailable to the resource allocator than are currently marked as such in the system agent code. This CL adds the following regions (documented in Intel docs #626540, #619503): 1. TSEG 2. GSM 3. DSM 4. PCH_RESERVED 5. CRAB_ABORT 6. APIC 7. TPM 8. LT_SECURITY Claimed regions before this change: ======================================================== base 0 size a0000 // 0 - > 0xa0000 base a0000 size 20000 // legacy VGA base c0000 size 40000 // RAM base c0000 size 76f40000 // 0xc0000 -> top_of_ram base 77000000 size 9400000 // top_of_ram -> TOLUD base c0000000 size 10000000 // PCIEXBAR base f8000000 size 2000000 // MMSPI base fb000000 size 1000 // REGBAR base fed80000 size 4000 // EDRAMBAR base fed84000 size 1000 // TBT0BAR base fed85000 size 1000 // TBT1BAR base fed86000 size 1000 // TBT2BAR base fed87000 size 1000 // TBT3BAR base fed90000 size 1000 // GFXVTBAR base fed91000 size 1000 // VTVC0BAR base fed92000 size 1000 // IPUVTBAR base feda0000 size 1000 // DMIBAR base feda1000 size 1000 // EPBAR base fedc0000 size 20000 // MCHBAR base 100000000 size 17fc00000 // 4GiB -> TOUUD Claimed regions with this change: ======================================================== base 0 size a0000 // 0 - > 0xa0000 base a0000 size 20000 // legacy VGA base c0000 size 40000 // RAM base c0000 size 76f40000 // 0xc0000 -> top_of_ram base 77000000 size 9400000 // top_of_ram -> TOLUD base 7b800000 size 800000 // TSEG base 7c000000 size 800000 // GSM base 7c800000 size 3c00000 // DSM base c0000000 size 10000000 // PCIEXBAR base f8000000 size 2000000 // MMSPI base fb000000 size 1000 // REGBAR base fc800000 size 2000000 // PCH_RESERVED base feb00000 size 80000 // CRAB_ABORT base fec00000 size 100000 // APIC base fed40000 size 10000 // TPM base fed50000 size 20000 // LT_SECURITY base fed80000 size 4000 // EDRAMBAR base fed84000 size 1000 // TBT0BAR base fed85000 size 1000 // TBT1BAR base fed86000 size 1000 // TBT2BAR base fed87000 size 1000 // TBT3BAR base fed90000 size 1000 // GFXVTBAR base fed91000 size 1000 // VTVC0BAR base fed92000 size 1000 // IPUVTBAR base feda0000 size 1000 // DMIBAR base feda1000 size 1000 // EPBAR base fedc0000 size 20000 // MCHBAR base 100000000 size 17fc00000 // 4GiB -> TOUUD BUG=b:149830546 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage' builds correctly. Tested on an Anahera device which successfully boots to ChromeOS with kernel version 5.10.109-15688-g857e654d1705. Also ran dmseg, and saw the added regions in e820 prints. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I058a5c1cc59703e35ceddb8a7e26fb22a6a2b75e Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15soc/intel/alderlake: remove unnecessary test conditionJeremy Compostella
mch_id is set to zero and then unnecessarily tested. TEST=build and boot image on ADL RVP board Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I20734e1638714027b976043b3a0457cbf3cd8442 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65121 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15soc/intel/alderlake: remove unnecessary MSR definitionJeremy Compostella
MSR_VR_MISC_CONFIG2 is not used by AlderLake code. TEST=compilation check Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/65120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-06-15soc/intel/alderlake/Kconfig: Unselect IPU for ADL-SMichał Żygowski
Alder Lake S CPUs do not have IPU device. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I79b084273f407119d903ed6f0cadf0084e8dda6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-10soc/intel/alderlake: Add Kconfig for Raptor LakeBora Guvendik
Until FSP for RPL and ADL align, mainboards using RPL should select SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together. Currently, ADL FSP headers and RPL FSP headers differ. Use RPL FSP header with Raptor Lake silicon. This code can be removed once ADL and RPL start using the same FSP. BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Iaf95352b9cafb81f23522bcf63753d199c0420eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-09soc/intel/alderlake: Drop enable_bios_reset_cpl() functionSubrata Banik
This patch drops enable_bios_reset_cpl() as FSP sets the BIOS Reset CPL before performing Graphics PM init (as part of FSP-S), hence, enable_bios_reset_cpl() function getting called inside systemagent.c is meaningless. Also, drop 1ms delay after setting the BIOS reset CPL. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I87beb444d3910f212a5a627cb449031db6cae38d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64837 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09soc/intel/alderlake: Add config option for S3 ACPISean Rhodes
Add Kconfig option `SOC_INTEL_ALDERLAKE_S3` which will adjust the ACPI to not offer D3Cold when using S3. This patch is the Alder Lake equivalent of CB:59024. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I04df8e106f9d53337b9eb5d2b9041b44a0e36684 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-09soc/intel/alderlake: add support for external source clockCliff Huang
Support up to 10 PCIe source clock out, including source clock out 7, 8, 9. This allows boards to use source clock 7, 8, 9. BUG=b:233252409 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63943 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-09soc/intel/alderlake: Add support for PCIe slot & device detect timeoutCliff Huang
1. add timeout for root port detection and pass to FSP. 2. add 'slot implemented' flag and pass to FSP. 3. PcieRpSlotImplemented needs to be set when the root port is set to hotplug. There is an assertion in FSP checking this. 4. PcieRpSlotImplemented is updated only when it is built-in as it is default to slot implemented in FSP. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-04soc/intel: Rename heci_init to cse_initSubrata Banik
This patch renames heci_init() to cse_init() as HECI initialization should have a bigger scope than just initializing the CSE (a.k.a HECI1 alone). BUG=none TEST=Able to build and boot google/taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic7edd55ccdcd70b244615fa06f81803a0ae6ce80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-02soc/intel/alderlake: add power limits for Alder Lake-N SKUsVidya Gopalakrishnan
This patch adds support for the ADL-N SKUs based on the PCH ID. Document reference: 645548 (ADL-N EDS Volume 1). BUG=None BRANCH=None TEST=Build FW and test on adln_rvp board Change-Id: I24c18a27a4a2c68c78bc3dc728c45ba04f57205d Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64472 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-06-02soc/intel/common/cpu: Use SoC overrides to set CPU privilege levelSubrata Banik
This patch implements a SoC overrides to set CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4584516102560e6bb2a4ae8c0d036be40ed96990 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-05-26soc/intel/alderlake: Hook up FSP hyper-threading setting to option APIFelix Singer
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Change-Id: I520a936b4c3a8997ba2c6bea0126b3bbcc5d68ce Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-25soc/intel/alderlake: Add chip config for DPA PreWakeleo.chou
The FSP includes a UPD to set the DPA (Dynamic Periodicity Alteration) PreWake value, which can be used to set the maximum pre-wake randomization time in "micro-ticks". This patch adds support for configuring that value. BUG=b:228410327 TEST=build FW and checked DPA value by fsp log. Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I08897c590a88aba058cb9e364185ea0794e1e7c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-24soc/intel/alderlake: Drop unused `PCH_DEV_SLOT_LPC` macroSubrata Banik
This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the Alder Lake SoC PCI device list. BUG=none TEST=Able to build and boot taeko, google board. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib2ae40fcc4499de34534f27f03b4c359c37409e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-18soc/intel/alderlake: Add support enable external V1P05/Vnn railsV Sowmya
This patch adds the support to enable the external V1P05/Vnn rails in S0 state via devicetree. BUG=b:223102016 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I555e5607af15a5f5d83ef74321b1b71f17cca289 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-18soc/intel/alderlake: Update the VccIn Aux Imon IccMaxV Sowmya
This patch updates the VccIn Aux Imon IccMax for ADL-N to SOC SKU specific value of 27A. Kit: 646929 - ADL N Platform Design Guide BUG=b:223102016 TEST=Verified that VccIn Aux Imon IccMax value is set to 27mA. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: If09cd1112fac9b30ff04c45aa5a6062c2513c715 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-18soc/intel/alderlake: Configure the SKU specific parameters for VR domainsV Sowmya
This patch configures the SKU specific power delivery parameters for the VR domains for ADL-N. +--------------+-------+-------+-------+-------+-----------+--------+ | SKU |Setting| AC LL | DC LL |ICC MAX|TDC Current|TDC Time| | | |(mOhms)|(mOhms)| (A) | (A) | (msec)| +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 081 | IA | 4.7 | 4.7 | 53 | 22 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 29 | 22 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 081(7W) | IA | 5.0 | 5.0 | 37 | 14 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 29 | 14 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 041(6W) | IA | 5.0 | 5.0 | 37 | 12 | 28000 | + Pentium +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 29 | 12 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 041(6W) | IA | 5.0 | 5.0 | 37 | 12 | 28000 | + Celeron +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 26 | 12 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 021(6W) | IA | 5.0 | 5.0 | 27 | 10 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 23 | 10 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ Kit: 646929 - ADL N Platform Design Guide -> Power_Map_Rev1p0 BUG=b:223102016 TEST=Boot and verify the UPD values are configured properly for ADL-N SKU's. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I3d6ae20323d3e859f52228822d4cbad143921a37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-16soc/intel: Add Raptor Lake device IDsBora Guvendik
Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs. References: RaptorLake External Design Specification Volume 1 (640555) 600/700 Series PCH External Design Specification Volume 1 (626817) Change-Id: I39e655dec2314a672ea63ba90d8bb3fc53bf77ba Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
2022-05-16soc/intel/*: Fix up header guardsArthur Heymans
Change-Id: If9ae375629c8af3d32b4c5493b5d63203e8847aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-16soc/intel/*: Use SSDT to pass A4GB and A4GSArthur Heymans
GNVS is more fragile as you need to keep struct elements in sync with ASL code. Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-16soc/inte/*/gpio; Add GPE_EN and GPE_STS register definitionMaulik V Vaghela
coreboot needs to set GPE_EN bit for the GPIOs which are wake capable from s0ix/sleep. Due to GPIO locking mechanism, coreboot/OS will not be able to write GPE_EN register post GPIO has been locked. This patch adds support in SoC code to provide correct offset for GPE_EN and GPE_STS registers to the common code. Plan is to use this offsets to set GPE_EN bits before GPIO locking in coreboot which will be part of subsequent CL. BUG=b:222375516 BRANCH=firmware-brya-14505.B TEST=Check if code compiles for Brya and correct offset values are printed. Change-Id: I6b813b30b8b360f8eccbf539b57387310e380560 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-15soc/intel/alderlake: Move array declarationArthur Heymans
Clang does not like array declarations inside plain switch cases. There are 2 options to fix this: use a block inside the switch statement, or declare it outside the switch statement. This does the latter. Change-Id: I9a02136fd63ac171b2bec4647c30c7eece930246 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-14soc/intel/alderlake: Fix Coverity CID 1488814Tarun Tuli
CID 1488814:  Uninitialized variables  (UNINIT) Commit c66ea98 introduced an issue after static analysis on merge. Because every APIC is associated with a CPU, this did not result in any issues at runtime but should be fixed/cleaned up. Now, the path name is initialized to null. Fixes: Coverity CID 1488814, commit c66ea98 TEST=Built on brya Change-Id: I0cfc8fd7a0c39e6610a9361630e3755293084f3d Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-13soc/intel/alderlake: Use correct formatted print for size_tArthur Heymans
Change-Id: Ifc0374ed49ecefc57dec8e72e73bac031838a9f5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64238 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12soc/intel/alderlake: provide a list of D-states to enter LPMTarun Tuli
Implement sub-function 1 (Get Device Constraints) of the Low Power S0 Idle Device-Specific Method (_DSM). This provides a way in which to describe various devices required D-states to enter LPM (S0ix). The information can be used to help in diagnostics and understanding of S0ix entry failure. Values were derived from Intel document 595644 (rev 0.45) and the ADL FSP sample ASL. This implementation adds support for ADL. Other SoC's could be ported to be included as well. If they aren't, they will default to the existing behavior of a single hardcoded device to ensure compatibility with Windows. TEST=Built and tested on brya by verifying SSDT contents Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao
2022-05-06soc/intel/alderlake: Add missing ACPI device path namesTarun Tuli
A few ACPI device path name handlers are missing. Add handling to ensure that these names are returned during acpi_device_path() calls. TEST=Built and tested on brya Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I37d6dd5df921c931af72dd469c3f4067c61b0df3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-05soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration doneSubrata Banik
This patch calls into the PMC IPC function that informs about PMC enumeration. Note: Alder Lake FSP Notify Phase 1 callback missed to send this PMC IPC, hence, this patch is considered as an improvement over FSP Notify Phase API. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS without any PMC IPC error. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I43cfad25a5861c5aa5dae293ff42c9cefe862ea2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-05-03soc/intel/alderlake: Update maximum PCIe and TBT ports and clocksMichał Żygowski
ADL-S CPU has maximum 3 PCIe interfaces when the x16 link is bifurcated into two x8 links. ADL-S PCH has up to 28 PCIe Root Ports, 18 CLKOUT and CLKREQ signals. ADL-S CPUs do not have Thunderbolt. Based on the Intel DOC #619501 and #619362. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I408c815d5a43c081beb3f84d795c2b863ce33eb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-29soc/{amd/stoneyridge,intel}: Don't select VBOOT_SEPARATE_VERSTAGEArthur Heymans
Now the bootblock is not limited to 64K so integrating vboot into the bootblock reduces the binary size. intel/apl is an exception since the bootblock size is limited to 32K. Change-Id: I5e02961183b5bcc37365458a3b10342e5bc2b525 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-29soc/intel: Decouple HECI disabling interface from HECI disable KconfigSubrata Banik
This patch decouples HECI disabling interface a.k.a SMM or PCR or PMC IPC etc. from DISABLE_HECI1_AT_PRE_BOOT kconfig as Intel ME BWG recommends to disable the CSE PCI device while CSE is in software temporary disable state. BUG=b:228789015 TEST=Able to build google/redrix. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I66abc04d5e195515165a77b0166d004f17d029e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-27soc/intel/cmn/lockdown: Perform SA lockdown configurationSubrata Banik
`sa_lockdown_cfg` function ensures locking the PAM register hence, skip dedicated calling into `sa_lock_pam()` from the SoC `finalize.c` file. Dropped sa_lock_pam() call from ADL/CNL/EHL/JSL and TGL. Additionally, this patch enforces SA lockdown configuration for SKL and ICL as well. BUG=b:211954778 TEST=Able to build google/brya with these changes. > localhost ~ # lspci -xxx | less 00:00.0 Host bridge: Device 8086:4601 (rev 04) Bit 0 for all PAM registers a.k.a, PAMx_0_0_0_PCI.LOCK bit is set (meaning locked). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-27soc/intel/alderlake: Skip FSP Notify API (post PCI enumeration)Subrata Banik
Alder Lake SoC deselects USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM Kconfig to skip FSP notify API (Post PCI Enumeration) and make use of native coreboot driver to perform SoC recommended operations prior booting to payload/OS. BUG=b:211954778 TEST=Able to build brya with these changes and coreboot log with this code change as below when ADL SoC selects required configs. [INFO ] coreboot skipped calling FSP notify phase: 00000020. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I46f6ca791fb60b417d205d0a54705f3481deebd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-04-27soc/intel/alderlake: Implement PCH lock down configurationSubrata Banik
This patch implements a function to enable IOSF Primary Trunk Clock Gating. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie28dde8f62adc5bafc4a42e608827f51da82570c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-04-27soc/intel/alderlake: Implement PMC feature lockSubrata Banik
This patch locks PMC features like: debug mode configuration and host read access to PMC XRAM. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I29178bdd9a94a24ca7056eb7377625f41a43c33c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-27soc/intel/alderlake: Implement PMC soft strap interface lockSubrata Banik
This patch performs locking of the PMC soft strap message interface. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Verified Bit 0 of PMC MMIO register 0x104c is set as below. > localhost ~ # iotools mmio_read32 0xfe00104c 0x00000001 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1ae972a203affa54c03de71f0f702356334cbf7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-27soc/intel/alderlake: Implement PMC static function lockSubrata Banik
This patch performs PMC static function lockdown. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Verified PMC static PG lock (bit 31) is set. > iotools mmio_read32 0xfe001e20 0x80000000 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I68343f9af4f34aceae06293c5f87c5eaa3430a60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-27soc/intel/adl/chip.h: Rename max_dram_speed to include unitsScott Chao
The unit of dram speed is MT/s so append it on variable name. BUG=b:229549930 BRANCH=none TEST=build coreboot without error Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I83c780440613050c0202f95d5f64991b61d9c280 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-23soc/intel/alderlake: Refactor `pmc_lockdown_cfg` functionSubrata Banik
This patch refactors the `pmc_lockdown_cfg()` to remove the helper functions and uses the `setbits32` function to enforce bit locking as applicable. BUG=b:211954778 TEST=Able to build google/redrix with these changes and boot to OS. > localhost ~ # iotools mmio_read32 0xfe0018c4 0x85000000 (bit 31 is set) > localhost ~ # iotools mmio_read32 0xfe001024 0x00062610 (bits 4, 17 and 18 are set) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic96da4638aa689b5fa47a3356986ca5a0343fe36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-22soc/intel: Remove unused <cbmem.h>Elyes HAOUAS
Change-Id: I529c822c9e952dae6613d3de64f6709e0fd9b385 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-20soc/intel: clean up dmi driver codeWonkyu Kim
1. Remove dmi.h as it's migrated as gpmr.header 2. Remove unused gpmr definitions 3. For old platforms, define DMI defintions in c code for less code changes. TEST=Build Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ib340ff1ab7fd88b1e7b3860ffec055a75e562de7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-19soc/intel/alderlake: Enable Pre Reset CPU TelemetryBora Guvendik
Insert CSE timestamps to coreboot timestamp table. BUG=b:182575295 TEST=Boot to OS on Brya Redrix board. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ifbea7155a294e0039a5bd1d16588775e90a29ae3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-13soc/intel/alderlake: Add support for UFS controllerMeera Ravindranath
UFS(Universal Flash Storage) is the next generation storage standard and a SCSI storage technology. It is also a successor of eMMC. Following changes are needed to add support for UFS - 1) Add UFS controller to chipset.cb and keep it off by default 2) Hook up FSP enable UPD for UFS #1 to the device from chipset.cb Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-13soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gatingSridhar Siricilla
The patch adds mechanism in the Alder Lake SoC code to control PCH USB2 Phy power gating from brya board variant's devicetree. Please refer Intel doc#723158 for more information. BUG=b:221461379 TEST=Build and boot Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-12soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spacesMichał Żygowski
PCH-S maps certain MMIO BARs differently than low power PCHs. The reserved ranges taken from Intel DOC #630603. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ifefedc629def207ecd6f7be792f6e12fb6016cc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decodingMichał Żygowski
Some Super I/Os may be strapped to respond on the secondary ports 0x4e/0x4f. Enable them early so that mainboard is able to initialize a serial port for example. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6df158f54a48fb9f3173a4b209316c8116aa265a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-11soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-SMichał Żygowski
According to Intel DOC #630603 P2SB BAR must be at 0xe0000000 for PCH-S. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie6db3f7108ff1edf62c94876412adfc6421034d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-11soc/intel/alderlake/include/soc/bootblock.h: Allow to build with PCH-SMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I1461a8cc3c131a6e2499df8e1ebc67f5fb3b9e35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-11soc/intel/alderlake: Select FSP2.3 for ADL-SMichał Żygowski
The FSP available at Intel R&DC kit #1000166 indicates FSP version 2.3 in the FSP headers. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I0af7faa603cb19b530513f531a28bd8b283baba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-11soc/intel/alderlake: Introduce PCH-S symbolMichał Żygowski
Introduce SOC_INTEL_ALDERLAKE_PCH_S symbol to differentiate from the low power chipsets. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I47676723747458b8b7fe726e900843c198901bda Reviewed-on: https://review.coreboot.org/c/coreboot/+/63455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUGSubrata Banik
This patch binds all FSP-M and FSP-S UPDs required for serial redirection with `FSP_ENABLE_SERIAL_DEBUG` config to allow coreboot to choose when to enable FSP debug output redirection to serial port. For example: PcdSerialDebugLevel => For controlling FSP debug level between FSP-M/S SerialDebugMrcLevel => For controllig MRC debug level. With this change FSP debug output will only be enabled when the user enables `FSP_ENABLE_SERIAL_DEBUG` from site-local config with coreboot serial image. BUG=b:225544587 TEST=Able to build and boot brya. Also, the FSP debug log is exactly the same before and with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I779c56b8b0fdebf45ea85b3b456a2d8066e26489 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63167 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-07soc/intel/alderlake: Hook up PAVP to KconfigLean Sheng Tan
Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital rights protection/management (DRM) technology for multimedia content) to Kconfig. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I5a364a9781642eb366e5e502a4ee69008c19bcd6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-07soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetreeLean Sheng Tan
The FSP needs to program VrPowerDeliverDesign configuration per platform according to the platform capabilities to avoid incorrect electrial/power parameters. This value is an enum of the available power delivery segments that are defined in the Platform Design Guide. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I74859e6735e59a15084a9e690b43f68341862833 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-07soc/intel/alderlake: Add support to update descriptor at runtimeReka Norman
On nereid, we need to update the descriptor based on fw_config (see the follow-up patch), so add support to update the descriptor at runtime. This is a temporary workaround while we find a better solution. This is basically adding back the configure_pmc_descriptor() function removed in CB:63339, just making it generic and allowing it to update multiple bytes at once. BUG=b:226848617 TEST=With the following patch, Type-C and HDMI work on nereid. Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc@google.com>
2022-04-07soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR KconfigSridhar Siricilla
The patch removes Kconfig CONFIG_ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR code which updates PMC descriptor for an intermediate ADL-P SoC stepping A0. Since intermediate ADL-P SoC is no longer supported and no board is selecting the Kconfig, so remove the code that updates PMC descriptor. TEST=Build and boot Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2a629353a4194a7505655346dcab4ef53059e0b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63339 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-06soc/intel/alderlake: Enable debug driver for Alder Lake platformSridhar Siricilla
The patch enables dynamic debug capability driver for Alder Lake platform. BUG=b:153410586 TEST= Build code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ic4df3d7f3d6585bd37c632b1a3f0a47c94b63697 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-06soc/intel/common: Abstract the common TCSS functionsJohn
This change abstracts the common TCSS functions for pad configuration and Thunderbolt authentication. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-05soc/intel/alderlake: Add HID for DPTF Battery ParticipantVarshit B Pandya
HID is defined in Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check BAT1 device HID Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Ie1fff53f938a5f13423e360c24c7181fa7613492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-04-04soc/intel/alderlake: Add new CPU IDLean Sheng Tan
Add new CPU ID 0x906A3 (L0 stepping). Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I280da46e5fdd3792df50556e2804b3bcb346eee3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63302 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-04soc/intel/alderlake: Update CPU IDs with correct steppingsLean Sheng Tan
Update ADL CPU IDs per correct steppings listed in Intel Doc 626774. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I722043c493b8c3de8965bcaa13f33c907d51f284 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-01soc/intel/alderlake: Add HID for DPTF Power ParticipantVarshit B Pandya
BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TPWR device HID Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I82507a3c0a521adbb8dec5520fd6d2ea3782c60e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-30soc/intel/alderlake: Log CSE RO write protection info for ADLSridhar Siricilla
The patch logs CSE RO's write protection information for Alder Lake platform. As part of write protection information, coreboot logs status on CSE RO write protection and range. Also, logs error message if EOM is disabled, and write protection for CSE RO is not enabled. TEST=Verify the write protection details on Gimble. Excerpt from Gimble coreboot log: [DEBUG] ME: WP for RO is enabled : YES [DEBUG] ME: RO write protection scope - Start=0x1000, End=0x15AFFF Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-29soc/intel: Move `pmc_clear_pmcon_sts()` into IA common codeSubrata Banik
This patch moves `pmc_clear_pmcon_sts` function into common code and remove SoC specific instances. Accessing PMC GEN_PMCON_A register differs between different Intel chipsets. Typically, there are two possible ways to perform GEN_PMCON_A register programming (like `pmc_clear_pmcon_sts()`) as: 1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration register. 2. Using MMIO access when GEN_PMCON_A is a memory mapped register. SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to perform GEN_PMCON_A register programming using PMC MMIO. BUG=b:211954778 TEST=Able to build brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeff Daly <jeffd@silicom-usa.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-03-28soc/intel/alderlake: Enable FSP_USES_CB_DEBUG_EVENT_HANDLER KconfigSubrata Banik
This patch uses the FSP event handler feature and updates with coreboot native debug implementation to unify the debug library between coreboot and FSP. BUG=b:225544587 TEST=Able to build and boot Brya with the same FSP debug log before and with this code changes. Before: Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000F961B000, size is 0x00150000, handle is 0xF961B000 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 With this code change: [SPEW ] Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE [SPEW ] Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 [SPEW ] Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A [SPEW ] The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000 [SPEW ] Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 [SPEW ] Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 [SPEW ] Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a0530a282657e379a00c3e7d0ed8148dd5e9196 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-28soc/intel/alderlake: Use coreboot native event handler for FSP-M/SSubrata Banik
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig is enabled. BUG=b:225544587 TEST=Able to build and boot brya. Also, verified the FSP debug log is exactly same before and with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I665def977faaae45f6f834d75e8456859093ba49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-22soc/intel/{adl,common}: Add ASPM setting in pcie_rp_configKevin Chang
This change provides config for devicetree to control ASPM per port BUG=b:220079865 TEST=Build FW and run stress exceed 2500 cycles on taeko. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62919 Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Martin L Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17soc/intel/adl: Remove IOM Mctp command from TCSS ASLMAULIK V VAGHELA
TCSS ASL code was carried forward from TGL and it used to follow the same sequence. Recently as part of s0ix hang issue, it was found that sending IOM MCTP command as part of TCSS D3 Cold enter-exit sequence created an issue. We discovered that due to change in hardware sequence, ADL should not set/reset IOM MCTP during D3 cold entry or exit. This patch removes the bit setting from ASL file to prevent hang in the system. This patch also removes obsolete Pcode mailbox communication which is no longer required for ADL. BUG=b:220796339 BRANCH=firmware-brya-14505.B TEST=Check if hang issue is resolved with the CL and no other regression observed Change-Id: I2f066bcc4a8f475a15ddd12ef5ed87d7298312bb Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62861 Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17soc/intel/alderlake/retimer: Change loglevel prefixWisley Chen
This message is not really an error message, so BIOS_ERR is inappropriate. Since the message is informational, switch to BIOS_INFO instead. BUG=b:222038287 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I9dc852a0cd30f95506c205f161a05e8a8c44fcd5 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17soc/intel/alderlake: Update ADL-P id list of th VccIn Aux Imon IccMax valuesCurtis Chen
Add ADL-P MCH ID 4, 8, 9, 10 into this list. BUG=b:222038287 BRANCH=firmware-brya-14505.B TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: I2cee31ba56e0b142c50a745c453968635e86296e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-15soc/intel/alderlake: Allow mainboard to configure c1-state auto-demotionMAULIK V VAGHELA
FSP has a parameter to enable/disable c1-state autodemotion feature. Boards/Baseboard can choose to use this feature as per requirement. This patch hooks up this parameter to devicetree BUG=b:221876248 BRANCH=firmware-brya-14505.B TEST=Check code compiles and correct value has been passed to FSP. Change-Id: I2d7839d8fecd7b5403f52f3926d1d0bc06728ed9 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-15soc/intel/adl/chip.h: Convert all camel case variables to snake caseMAULIK V VAGHELA
coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-15{mb, soc}: Move mrc_cache invalidating logic into `memory` common codeSubrata Banik
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced per mainboard logic to invalidate the mrc_cache. This patch moves mrc_cache invalidating logic into IA common code and cleans up the code to remove unused argument `dimms_changed` from SoC and mainboard directory. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15soc/intel/common: Pass `FSPM_UPD *` argument for spd functionsSubrata Banik
This patch adds `FSPM_UPD *` as argument for mem_populate_channel_data() and read_spd_dimm(). This change will help to update the architectural FSP-M UPDs in read_spd_dimm(). BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I770cfd05194c33e11f98f95c5b93157b0ead70c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototypeSubrata Banik
This patch modifies `memcfg_init` and `variant_memory_init`functions argument from FSP_M_CONFIG to FSPM_UPD. This change in `memcfg_init()` argument will help to update the architectural FSP-M UPDs from common code blocks rather than going into SoC and/or mainboard implementation. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-14soc/intel/alderlake: Add EPP override supportCliff Huang
This updates energy performance preference value to all logical CPUs when the corresponding chip config is true. BUG=b:219785001 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-10soc/intel/alderlake: Inject CSE TS into CBMEM timestamp tableBora Guvendik
Get boot performance timestamps from CSE and inject them into CBMEM timestamp table after normalizing to the zero-point value. Although consumer CSE sku also supports this feature, it was validated on CSE Lite sku only. BUG=b:182575295 TEST=Able to see TS elapse prior to IA reset on Brya/Redrix 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 88,000 945:CSE started to handle ICC configuration 88,000 (0) 946:CSE sent 'Host BIOS Prep Done' to PMC 90,000 (2,000) 947:CSE received 'CPU Reset Done Ack sent' from PMC 282,000 (192,000) 0:1st timestamp 330,857 (48,857) 11:start of bootblock 341,811 (10,953) 12:end of bootblock 349,299 (7,487) Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-10soc/intel/adl: Send EOP early in the boot sequenceMAULIK V VAGHELA
As part of boot time optimization, one of the culprit was CSE where response to End Of Post (EOP) command used to take ~60ms. Earlier patch was pushed to delay the EOP to reduce response time to ~5-7 ms. During this stage overall platform boot time was ~1.15 seconds. Once boot time was optimized to ~ 1 seconds, CSE EOP time again increased to ~80 ms since coreboot used to send EOP at the time where CSE was busy. This created some back and forth moving of sending EOP command function within coreboot sequence. Upon debugging using traces, it was found that coreboot used to send EOP late where CSE was busy loading other IP payload, so it might take more time to respond. In order to avoid delayed response, coreboot has to send EOP in stage when CSE is done with firmware init and it will be ready to serve EOP as soon as possible. This also aligns with previous flow where FSP used to send EOP once silicon init is done and coreboot used to rely on FSP to send this message. Moving EOP to earlier stage (From SoC) meets the requirement and CSE EOP time reduces from ~60 ms to ~20 ms on Brya board. Note that once SoC code sends EOP, coreboot common code won't send it again since common code already has check in case EOP is sent earlier. BUG=b:211085685 BRANCH=firmware-brya-14505.B TEST=Tested on Brya system before and after the changes. Observed ~40ms savings in boot time. Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-03-09drivers/wifi,soc/intel/adl: Move CnviDdrRfim property to driversTim Wawrzynczak
Some non-SoC code might want to know whether or not the CNVi DDR RFIM feature is enabled. Also note that future SoCs may also support this feature. To make the CnviDdrRfim property generic, move it from soc/intel/alderlake to drivers/wifi/generic instead. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idf9fba0a79d1f431269be5851b026ed966600160 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
2022-03-08timestamps: Rename timestamps to make names more consistentJakub Czapiga
This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-07soc/intel/alderlake: Use Kconfigs for Descriptor RegionSridhar Siricilla
The patch uses Kconfigs for Descriptor Region and Descriptor Region size instead of locally defined macros TEST=Build and boot Brya board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I3f9461c8604383f995a4438f45286b14fb94deaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/62264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2022-03-07soc/intel/alderlake: Define Kconfigs for Descriptor RegionSridhar Siricilla
The patch defines Kconfigs for FMAP Descriptor Region and Descriptor Region size. The Kconfigs will be used by follow-up patches. TEST=Build Brya code Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ia3481acefbda885617607675aef2afbb81c21c77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-03-02mb, soc: Add the SPD_CACHE_ENABLEZhuohao Lee
In order to cache the spd data which reads from the memory module, we add SPD_CACHE_ENABLE option to enable the cache for the spd data. If this option is enabled, the RW_SPD_CACHE region needs to be added to the flash layout for caching the data. Since the user may remove the memory module after the bios caching the data, we need to add the invalidate flag to invalidate the mrc cache. Otherwise, the bios will use the mrc cache and can make the device malfunction. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass and enable this feature to the brask the device could speed up around 150ms with this feature. Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25mb, soc: change mainboard_memory_init_params prototypeZhuohao Lee
The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the input which make the board has no chance to modify data in the FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on its requirement. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-25intelblocks/pcie: Correct mapping between LCAP port and coreboot indexMAULIK V VAGHELA
coreboot uses port index which is 0 based for all PCIe root ports. In case of PCIe remapping logic, coreboot reads LCAP register from PCIe configuration space which contains port number (mostly 1 based). This assumption might not be true for all the ports in coreboot. TBT's LCAP registers are returning port index which are based on 2. coreboot's PCIe remapping logic returns port index based on index 1. This patch adds variable to pcie_rp_config to pass lcap_port_base to the pcie remapping function, so coreboot can map any n-based LCAP encoding to 0-based indexing scheme. This patch updates correct lcap_port_base variable for all PCIe root ports for all SOCs, so that function returns correct 0-based index from LCAP port number. BUG=b:210933428 BRANCH=None TEST=Check if code compiles for all ADL boards Change-Id: I7f9c3c8e753b982e2ede1a41bf87d6355b82da0f Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61936 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25arch/x86: factor out and commonize HPET_BASE_ADDRESS definitionFelix Held
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000, so define this once in arch/x86 and include this wherever needed. The old AMD AGESA code in vendorcode that has its own definition is left unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common definition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-02-21soc/intel/alderlake: Make clang static assert happyArthur Heymans
Change-Id: Ia3cd66f6b735f7430abcdba8a9323d5ee1320fd4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21soc/intel/alderlake: Fix function pointer typeArthur Heymans
const void is not a proper return type for a function. It's the function pointer themselves that need to be const. This fixes building with clang. Change-Id: I99888ab9d9d80f1d6edb33b9f4a3f556f211a6e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21soc/intel/adl/bootblock/report_platform.c: Use the correct formatArthur Heymans
Change-Id: I54c40434f44621c4ea6564ac9c87c5b2fa083b5d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21soc/intel/alderlake: Enable eMMC based on dev enabledKrishna Prasad Bhat
1. Add eMMC device function in pci_devs.h. 2. Enable eMMC device and configuration based on dev enabled. 3. Add SOC acpi name for eMMC. Change-Id: I44f17420f7a2a1ca0fbb6cfb1886b1617c5a5064 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 13:10:08 +0000