diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-03-10 17:53:14 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-03-15 10:17:25 +0000 |
| commit | 2eb51aace5489b2f2d20e510f19a1e3b17bf1d60 (patch) | |
| tree | 9bf2dcdc8ca37ca5aa4c49a24c0c5e764928d7f1 /src/soc/intel/alderlake | |
| parent | 5730d018d1395cf68c2fe0e795831f6780c734de (diff) | |
{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype
This patch modifies `memcfg_init` and `variant_memory_init`functions
argument from FSP_M_CONFIG to FSPM_UPD.
This change in `memcfg_init()` argument will help to update the
architectural FSP-M UPDs from common code blocks rather than going
into SoC and/or mainboard implementation.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/meminit.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/meminit.c | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index 98482e33cc..6af0accb1b 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -109,7 +109,7 @@ struct mb_cfg { uint8_t LpDdrDqDqsReTraining; }; -void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, +void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated, bool *dimms_changed); #endif /* _SOC_ALDERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 8b54cb190e..31b3ae1cfa 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -235,11 +235,12 @@ static void ddr5_fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cf mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true); } -void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, +void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated, bool *dimms_changed) { struct mem_channel_data data; bool dq_dqs_auto_detect = false; + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; mem_cfg->ECT = mb_cfg->ect; mem_cfg->UserBd = mb_cfg->UserBd; |