diff options
| author | Cliff Huang <cliff.huang@intel.corp-partner.google.com> | 2022-06-21 09:43:20 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-22 17:32:00 +0000 |
| commit | 7b4643f5fa170d49217ace787bd00fba0b6c1acc (patch) | |
| tree | 610a4ab2da2f74cb4f6be54e2e1d29f98335bd70 /src/soc/intel/alderlake | |
| parent | 88f863cfbb1f3f547cf503b462e29c285e8f1c94 (diff) | |
soc/intel/alderlake: Remove menu option for MAX_PCIE_CLOCK_SRC
MAX_PCIE_CLOCK_SRC is not an user-configurable option.
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: Ia49f6e236e8853c377e9096500d96f21dbdc9b8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65298
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 58656df8f7..3177a45902 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -242,7 +242,6 @@ config MAX_ROOT_PORTS default MAX_PCH_ROOT_PORTS config MAX_PCIE_CLOCK_SRC - prompt "Number of Source Clock supported from SOC" int default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 5 if SOC_INTEL_ALDERLAKE_PCH_N |