src: Make PCI ID define names shorter

Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.

Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'

* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'

Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>

5 files changed, 169 insertions, 169 deletions

diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c
index 6b526f12ef..3342e4b732 100644
--- a/src/soc/intel/alderlake/bootblock/report_platform.c
+++ b/src/soc/intel/alderlake/bootblock/report_platform.c
@@ -34,21 +34,21 @@ static struct {
 	u16 mchid;
 	const char *name;
 } mch_table[] = {
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, "Alderlake-P" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, "Alderlake-P" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_4, "Alderlake-P" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, "Alderlake-P" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, "Alderlake-P" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, "Alderlake-P" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_8, "Alderlake-P" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_9, "Alderlake-P" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_10, "Alderlake-P" },
-	{ PCI_DEVICE_ID_INTEL_ADL_M_ID_1, "Alderlake-M" },
-	{ PCI_DEVICE_ID_INTEL_ADL_M_ID_2, "Alderlake-M" },
-	{ PCI_DEVICE_ID_INTEL_ADL_N_ID_1, "Alderlake-N" },
-	{ PCI_DEVICE_ID_INTEL_ADL_N_ID_2, "Alderlake-N" },
-	{ PCI_DEVICE_ID_INTEL_ADL_N_ID_3, "Alderlake-N" },
-	{ PCI_DEVICE_ID_INTEL_ADL_N_ID_4, "Alderlake-N" },
+	{ PCI_DID_INTEL_ADL_P_ID_1, "Alderlake-P" },
+	{ PCI_DID_INTEL_ADL_P_ID_3, "Alderlake-P" },
+	{ PCI_DID_INTEL_ADL_P_ID_4, "Alderlake-P" },
+	{ PCI_DID_INTEL_ADL_P_ID_5, "Alderlake-P" },
+	{ PCI_DID_INTEL_ADL_P_ID_6, "Alderlake-P" },
+	{ PCI_DID_INTEL_ADL_P_ID_7, "Alderlake-P" },
+	{ PCI_DID_INTEL_ADL_P_ID_8, "Alderlake-P" },
+	{ PCI_DID_INTEL_ADL_P_ID_9, "Alderlake-P" },
+	{ PCI_DID_INTEL_ADL_P_ID_10, "Alderlake-P" },
+	{ PCI_DID_INTEL_ADL_M_ID_1, "Alderlake-M" },
+	{ PCI_DID_INTEL_ADL_M_ID_2, "Alderlake-M" },
+	{ PCI_DID_INTEL_ADL_N_ID_1, "Alderlake-N" },
+	{ PCI_DID_INTEL_ADL_N_ID_2, "Alderlake-N" },
+	{ PCI_DID_INTEL_ADL_N_ID_3, "Alderlake-N" },
+	{ PCI_DID_INTEL_ADL_N_ID_4, "Alderlake-N" },
 
 };
 
@@ -56,76 +56,76 @@ static struct {
 	u16 espiid;
 	const char *name;
 } pch_table[] = {
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_0, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_1, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_2, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_3, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_4, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_5, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_6, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_7, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_8, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_9, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_10, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_11, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_12, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_13, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_14, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_15, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_16, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_17, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_18, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_19, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_20, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_21, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_22, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_23, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_24, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_25, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_26, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_27, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_28, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33, "Alderlake-P SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_M_ESPI_32, "Alderlake-M SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_1, "Alderlake-N SKU" },
-	{ PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_2, "Alderlake-N SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_0, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_1, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_2, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_3, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_4, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_5, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_6, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_7, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_8, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_9, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_10, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_11, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_12, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_13, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_14, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_15, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_16, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_17, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_18, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_19, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_20, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_21, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_22, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_23, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_24, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_25, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_26, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_27, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_28, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_29, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_30, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_31, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_32, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_P_ESPI_33, "Alderlake-P SKU" },
+	{ PCI_DID_INTEL_ADP_M_ESPI_32, "Alderlake-M SKU" },
+	{ PCI_DID_INTEL_ADP_M_N_ESPI_1, "Alderlake-N SKU" },
+	{ PCI_DID_INTEL_ADP_M_N_ESPI_2, "Alderlake-N SKU" },
 };
 
 static struct {
 	u16 igdid;
 	const char *name;
 } igd_table[] = {
-	{ PCI_DEVICE_ID_INTEL_ADL_GT0, "Alderlake GT0" },
-	{ PCI_DEVICE_ID_INTEL_ADL_GT1, "Alderlake GT1" },
-	{ PCI_DEVICE_ID_INTEL_ADL_GT1_1, "Alderlake GT1" },
-	{ PCI_DEVICE_ID_INTEL_ADL_GT1_2, "Alderlake GT1" },
-	{ PCI_DEVICE_ID_INTEL_ADL_GT1_3, "Alderlake GT1" },
-	{ PCI_DEVICE_ID_INTEL_ADL_GT1_4, "Alderlake GT1" },
-	{ PCI_DEVICE_ID_INTEL_ADL_GT1_5, "Alderlake GT1" },
-	{ PCI_DEVICE_ID_INTEL_ADL_GT1_6, "Alderlake GT1" },
-	{ PCI_DEVICE_ID_INTEL_ADL_GT1_7, "Alderlake GT1" },
-	{ PCI_DEVICE_ID_INTEL_ADL_GT1_8, "Alderlake GT1" },
-	{ PCI_DEVICE_ID_INTEL_ADL_GT1_9, "Alderlake GT1" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_GT2, "Alderlake P GT2" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_1, "Alderlake P GT2" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_2, "Alderlake P GT2" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_3, "Alderlake P GT2" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_4, "Alderlake P GT2" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_5, "Alderlake P GT2" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_6, "Alderlake P GT2" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_7, "Alderlake P GT2" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_8, "Alderlake P GT2" },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_GT2_9, "Alderlake P GT2" },
-	{ PCI_DEVICE_ID_INTEL_ADL_M_GT1, "Alderlake M GT1" },
-	{ PCI_DEVICE_ID_INTEL_ADL_M_GT2, "Alderlake M GT2" },
-	{ PCI_DEVICE_ID_INTEL_ADL_M_GT3, "Alderlake M GT3" },
-	{ PCI_DEVICE_ID_INTEL_ADL_N_GT1, "Alderlake N GT1" },
-	{ PCI_DEVICE_ID_INTEL_ADL_N_GT2, "Alderlake N GT2" },
-	{ PCI_DEVICE_ID_INTEL_ADL_N_GT3, "Alderlake N GT3" },
+	{ PCI_DID_INTEL_ADL_GT0, "Alderlake GT0" },
+	{ PCI_DID_INTEL_ADL_GT1, "Alderlake GT1" },
+	{ PCI_DID_INTEL_ADL_GT1_1, "Alderlake GT1" },
+	{ PCI_DID_INTEL_ADL_GT1_2, "Alderlake GT1" },
+	{ PCI_DID_INTEL_ADL_GT1_3, "Alderlake GT1" },
+	{ PCI_DID_INTEL_ADL_GT1_4, "Alderlake GT1" },
+	{ PCI_DID_INTEL_ADL_GT1_5, "Alderlake GT1" },
+	{ PCI_DID_INTEL_ADL_GT1_6, "Alderlake GT1" },
+	{ PCI_DID_INTEL_ADL_GT1_7, "Alderlake GT1" },
+	{ PCI_DID_INTEL_ADL_GT1_8, "Alderlake GT1" },
+	{ PCI_DID_INTEL_ADL_GT1_9, "Alderlake GT1" },
+	{ PCI_DID_INTEL_ADL_P_GT2, "Alderlake P GT2" },
+	{ PCI_DID_INTEL_ADL_P_GT2_1, "Alderlake P GT2" },
+	{ PCI_DID_INTEL_ADL_P_GT2_2, "Alderlake P GT2" },
+	{ PCI_DID_INTEL_ADL_P_GT2_3, "Alderlake P GT2" },
+	{ PCI_DID_INTEL_ADL_P_GT2_4, "Alderlake P GT2" },
+	{ PCI_DID_INTEL_ADL_P_GT2_5, "Alderlake P GT2" },
+	{ PCI_DID_INTEL_ADL_P_GT2_6, "Alderlake P GT2" },
+	{ PCI_DID_INTEL_ADL_P_GT2_7, "Alderlake P GT2" },
+	{ PCI_DID_INTEL_ADL_P_GT2_8, "Alderlake P GT2" },
+	{ PCI_DID_INTEL_ADL_P_GT2_9, "Alderlake P GT2" },
+	{ PCI_DID_INTEL_ADL_M_GT1, "Alderlake M GT1" },
+	{ PCI_DID_INTEL_ADL_M_GT2, "Alderlake M GT2" },
+	{ PCI_DID_INTEL_ADL_M_GT3, "Alderlake M GT3" },
+	{ PCI_DID_INTEL_ADL_N_GT1, "Alderlake N GT1" },
+	{ PCI_DID_INTEL_ADL_N_GT2, "Alderlake N GT2" },
+	{ PCI_DID_INTEL_ADL_N_GT3, "Alderlake N GT3" },
 };
 
 static inline uint8_t get_dev_revision(pci_devfn_t dev)
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index aad45df3cf..67664061c8 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -48,19 +48,19 @@ static const struct {
 	enum soc_intel_alderlake_power_limits limits;
 	enum soc_intel_alderlake_cpu_tdps cpu_tdp;
 } cpuid_to_adl[] = {
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_10, ADL_P_142_242_282_15W_CORE, TDP_15W },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, ADL_P_142_242_282_15W_CORE, TDP_15W },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, ADL_P_142_242_282_15W_CORE, TDP_15W },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, ADL_P_282_482_28W_CORE, TDP_28W },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_282_482_28W_CORE, TDP_28W },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_442_482_45W_CORE, TDP_45W },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_4, ADL_P_642_682_45W_CORE, TDP_45W },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_642_682_45W_CORE, TDP_45W },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, ADL_P_442_482_45W_CORE, TDP_45W },
-	{ PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W },
-	{ PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W },
-	{ PCI_DEVICE_ID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W },
+	{ PCI_DID_INTEL_ADL_P_ID_10, ADL_P_142_242_282_15W_CORE, TDP_15W },
+	{ PCI_DID_INTEL_ADL_P_ID_7, ADL_P_142_242_282_15W_CORE, TDP_15W },
+	{ PCI_DID_INTEL_ADL_P_ID_6, ADL_P_142_242_282_15W_CORE, TDP_15W },
+	{ PCI_DID_INTEL_ADL_P_ID_7, ADL_P_282_482_28W_CORE, TDP_28W },
+	{ PCI_DID_INTEL_ADL_P_ID_5, ADL_P_282_482_28W_CORE, TDP_28W },
+	{ PCI_DID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W },
+	{ PCI_DID_INTEL_ADL_P_ID_5, ADL_P_442_482_45W_CORE, TDP_45W },
+	{ PCI_DID_INTEL_ADL_P_ID_4, ADL_P_642_682_45W_CORE, TDP_45W },
+	{ PCI_DID_INTEL_ADL_P_ID_3, ADL_P_642_682_45W_CORE, TDP_45W },
+	{ PCI_DID_INTEL_ADL_P_ID_1, ADL_P_442_482_45W_CORE, TDP_45W },
+	{ PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W },
+	{ PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W },
+	{ PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W },
 };
 
 /* Types of display ports */
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 426f6216b6..66db16b6ed 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -174,43 +174,43 @@ void soc_init_cpus(struct bus *cpu_bus)
 enum adl_cpu_type get_adl_cpu_type(void)
 {
 	const uint16_t adl_m_mch_ids[] = {
-		PCI_DEVICE_ID_INTEL_ADL_M_ID_1,
-		PCI_DEVICE_ID_INTEL_ADL_M_ID_2,
+		PCI_DID_INTEL_ADL_M_ID_1,
+		PCI_DID_INTEL_ADL_M_ID_2,
 	};
 	const uint16_t adl_p_mch_ids[] = {
-		PCI_DEVICE_ID_INTEL_ADL_P_ID_1,
-		PCI_DEVICE_ID_INTEL_ADL_P_ID_3,
-		PCI_DEVICE_ID_INTEL_ADL_P_ID_4,
-		PCI_DEVICE_ID_INTEL_ADL_P_ID_5,
-		PCI_DEVICE_ID_INTEL_ADL_P_ID_6,
-		PCI_DEVICE_ID_INTEL_ADL_P_ID_7,
-		PCI_DEVICE_ID_INTEL_ADL_P_ID_8,
-		PCI_DEVICE_ID_INTEL_ADL_P_ID_9,
-		PCI_DEVICE_ID_INTEL_ADL_P_ID_10
+		PCI_DID_INTEL_ADL_P_ID_1,
+		PCI_DID_INTEL_ADL_P_ID_3,
+		PCI_DID_INTEL_ADL_P_ID_4,
+		PCI_DID_INTEL_ADL_P_ID_5,
+		PCI_DID_INTEL_ADL_P_ID_6,
+		PCI_DID_INTEL_ADL_P_ID_7,
+		PCI_DID_INTEL_ADL_P_ID_8,
+		PCI_DID_INTEL_ADL_P_ID_9,
+		PCI_DID_INTEL_ADL_P_ID_10
 	};
 	const uint16_t adl_s_mch_ids[] = {
-		PCI_DEVICE_ID_INTEL_ADL_S_ID_1,
-		PCI_DEVICE_ID_INTEL_ADL_S_ID_2,
-		PCI_DEVICE_ID_INTEL_ADL_S_ID_3,
-		PCI_DEVICE_ID_INTEL_ADL_S_ID_4,
-		PCI_DEVICE_ID_INTEL_ADL_S_ID_5,
-		PCI_DEVICE_ID_INTEL_ADL_S_ID_6,
-		PCI_DEVICE_ID_INTEL_ADL_S_ID_7,
-		PCI_DEVICE_ID_INTEL_ADL_S_ID_8,
-		PCI_DEVICE_ID_INTEL_ADL_S_ID_9,
-		PCI_DEVICE_ID_INTEL_ADL_S_ID_10,
-		PCI_DEVICE_ID_INTEL_ADL_S_ID_11,
-		PCI_DEVICE_ID_INTEL_ADL_S_ID_12,
-		PCI_DEVICE_ID_INTEL_ADL_S_ID_13,
-		PCI_DEVICE_ID_INTEL_ADL_S_ID_14,
-		PCI_DEVICE_ID_INTEL_ADL_S_ID_15,
+		PCI_DID_INTEL_ADL_S_ID_1,
+		PCI_DID_INTEL_ADL_S_ID_2,
+		PCI_DID_INTEL_ADL_S_ID_3,
+		PCI_DID_INTEL_ADL_S_ID_4,
+		PCI_DID_INTEL_ADL_S_ID_5,
+		PCI_DID_INTEL_ADL_S_ID_6,
+		PCI_DID_INTEL_ADL_S_ID_7,
+		PCI_DID_INTEL_ADL_S_ID_8,
+		PCI_DID_INTEL_ADL_S_ID_9,
+		PCI_DID_INTEL_ADL_S_ID_10,
+		PCI_DID_INTEL_ADL_S_ID_11,
+		PCI_DID_INTEL_ADL_S_ID_12,
+		PCI_DID_INTEL_ADL_S_ID_13,
+		PCI_DID_INTEL_ADL_S_ID_14,
+		PCI_DID_INTEL_ADL_S_ID_15,
 	};
 
 	const uint16_t adl_n_mch_ids[] = {
-		PCI_DEVICE_ID_INTEL_ADL_N_ID_1,
-		PCI_DEVICE_ID_INTEL_ADL_N_ID_2,
-		PCI_DEVICE_ID_INTEL_ADL_N_ID_3,
-		PCI_DEVICE_ID_INTEL_ADL_N_ID_4,
+		PCI_DID_INTEL_ADL_N_ID_1,
+		PCI_DID_INTEL_ADL_N_ID_2,
+		PCI_DID_INTEL_ADL_N_ID_3,
+		PCI_DID_INTEL_ADL_N_ID_4,
 	};
 
 	const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT),
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index dac36934df..b4e833bf55 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -309,17 +309,17 @@ static uint16_t get_vccin_aux_imon_iccmax(void)
 	}
 
 	switch (mch_id) {
-	case PCI_DEVICE_ID_INTEL_ADL_P_ID_1:
-	case PCI_DEVICE_ID_INTEL_ADL_P_ID_3:
-	case PCI_DEVICE_ID_INTEL_ADL_P_ID_5:
-	case PCI_DEVICE_ID_INTEL_ADL_P_ID_6:
-	case PCI_DEVICE_ID_INTEL_ADL_P_ID_7:
+	case PCI_DID_INTEL_ADL_P_ID_1:
+	case PCI_DID_INTEL_ADL_P_ID_3:
+	case PCI_DID_INTEL_ADL_P_ID_5:
+	case PCI_DID_INTEL_ADL_P_ID_6:
+	case PCI_DID_INTEL_ADL_P_ID_7:
 		tdp = get_cpu_tdp();
 		if (tdp == TDP_45W)
 			return ICC_MAX_TDP_45W;
 		return ICC_MAX_TDP_15W_28W;
-	case PCI_DEVICE_ID_INTEL_ADL_M_ID_1:
-	case PCI_DEVICE_ID_INTEL_ADL_M_ID_2:
+	case PCI_DID_INTEL_ADL_M_ID_1:
+	case PCI_DID_INTEL_ADL_M_ID_2:
 		return ICC_MAX_ID_ADL_M_MA;
 	default:
 		printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n",
diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c
index c0058cdba6..58c77f76d1 100644
--- a/src/soc/intel/alderlake/vr_config.c
+++ b/src/soc/intel/alderlake/vr_config.c
@@ -59,55 +59,55 @@ static uint32_t load_table(const struct vr_lookup *tbl, const int tbl_entries, c
 
 /* Per the power map from #613643, update ADL-P 6+8+2 (28W) VR configuration */
 static const struct vr_lookup vr_config_ll[] = {
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
+	{ PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
+	{ PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
+	{ PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
+	{ PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
+	{ PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
+	{ PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
+	{ PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) },
+	{ PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
+	{ PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
+	{ PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) },
 };
 
 static const struct vr_lookup vr_config_icc[] = {
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_ICC(109, 55) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
+	{ PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) },
+	{ PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
+	{ PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) },
+	{ PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_ICC(120, 55) },
+	{ PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_ICC(109, 55) },
+	{ PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) },
+	{ PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_ICC(85, 55) },
+	{ PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
+	{ PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
+	{ PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) },
 };
 
 static const struct vr_lookup vr_config_tdc_timewindow[] = {
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
+	{ PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) },
 };
 
 static const struct vr_lookup vr_config_tdc_currentlimit[] = {
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
-	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
+	{ PCI_DID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) },
+	{ PCI_DID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) },
+	{ PCI_DID_INTEL_ADL_P_ID_4, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) },
+	{ PCI_DID_INTEL_ADL_P_ID_5, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(47, 47) },
+	{ PCI_DID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) },
+	{ PCI_DID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) },
+	{ PCI_DID_INTEL_ADL_P_ID_7, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(32, 32) },
+	{ PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
+	{ PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
+	{ PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) },
 };
 
 void fill_vr_domain_config(FSP_S_CONFIG *s_cfg,