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path: root/src/northbridge/intel
AgeCommit message (Expand)Author
2016-09-15northbridge/intel/nehalem/gma.c: Improve code formattingElyes HAOUAS
2016-09-13i945.h: fix #include pathAntonello Dettori
2016-09-13northbridge/intel/nehalem: transition away from device_tAntonello Dettori
2016-09-13northbridge/intel/gm45: transation away from device_tFurquan Shaikh
2016-09-12src/northbridge: Improve code formattingElyes HAOUAS
2016-09-10northbridge/intel/x4x: transition away from device_tAntonello Dettori
2016-09-10northbridge/intel/i5000: transition away from device_tAntonello Dettori
2016-09-10northbridge/intel/e7505: transition away from device_tAntonello Dettori
2016-09-09northbridge/intel/fsp_rangeley: transition away from device_tAntonello Dettori
2016-09-09nb/intel/gm45: Fix DMAR table - IOMMU advertisement for ME interfacesDamien Zammit
2016-09-07nb/intel/x4x: Correct typos in interrupt routing for PEGDamien Zammit
2016-09-07nb/intel/x4x: Turn on PEG graphics in device enableDamien Zammit
2016-09-07nb/intel/x4x: Increase MMIO PCI space to 2GiBDamien Zammit
2016-09-07nb/intel/x4x: Fix DMI initDamien Zammit
2016-09-07gm45/gma.c: clean up some registersArthur Heymans
2016-09-04northbridge/intel/i945: transition away from device_tAntonello Dettori
2016-09-04northbridge/intel/sandybridge: transition away from device_tAntonello Dettori
2016-08-31northbridge/intel: Add required space before opening parenthesis '('Elyes HAOUAS
2016-08-31i945: Enable changing VRAM sizeArthur Heymans
2016-08-23src/northbridge: Remove unnecessary whitespace before "\n" and "\t"Elyes HAOUAS
2016-08-09x4x: make preallocated IGD memory a cmos optionArthur Heymans
2016-08-09x4x: add non documented vram sizesArthur Heymans
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
2016-07-31src/northbridge: Capitalize CPU, RAM and ROMElyes HAOUAS
2016-07-28bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh
2016-07-27nb/intel/x4x: Fix CAS latency detection and max memory detectionDamien Zammit
2016-07-26intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZEKyösti Mälkki
2016-07-19nb/intel/x4x: Fix CAS latency detectionDamien Zammit
2016-07-15intel/x4x: Do not use scratchpad register for ACPI S3Kyösti Mälkki
2016-07-15intel/pineview: Do not use scratchpad register for ACPI S3Kyösti Mälkki
2016-07-14nb/intel/pineview/northbridge.c: Remove legacy_hole_size_k declarationJonathan Neuschäfer
2016-07-09nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAMDamien Zammit
2016-07-07intel/sandybridge: read correct leaf for cpu familyRyan Salsamendi
2016-06-26intel/i945: Use common ACPI S3 recoveryKyösti Mälkki
2016-06-23intel/sandybridge: Fix builds with System Agent blobKyösti Mälkki
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
2016-06-22intel/model_206ax: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
2016-06-20nb/intel/sandybridge/raminit: Use supported CASPatrick Rudolph
2016-06-20nb/intel/sandybridge/raminit: Do code cleanupPatrick Rudolph
2016-06-20nb/intel/sandybridge/raminit: Do code cleanupPatrick Rudolph
2016-06-20nb/intel/sandybridge/raminit: Allow 933Mhz on Lenovo devicesPatrick Rudolph
2016-06-17intel/model_206ax: Move platform specific definesKyösti Mälkki
2016-06-17Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki
2016-06-12nb/intel/raminit (native): Read PCI mmio size from devicetreePatrick Rudolph
2016-06-12nb/intel: Factor out common MRC codePatrick Rudolph
2016-06-04nb/intel/x4x: Fix unpopulated valueDamien Zammit
2016-06-04gm45: enable setting all vram sizes from cmosArthur Heymans
2016-05-31nb/intel/x4x: Add DMI/EP initDamien Zammit
2016-05-31Fix leaking CONFIG_VGA=yKyösti Mälkki
2016-05-17intel/sch: Merge northbridge and southbridge in src/socStefan Reinauer
2016-05-08intel/pineview: Don't try to store 34 bits in 32Stefan Reinauer
2016-05-04nb/intel/sandybridge/raminit: support calling dram_freq multiple timesPatrick Rudolph
2016-05-04nb/intel/sandybridge/raminit: add additional fallbacksPatrick Rudolph
2016-05-04nb/intel/gm45: Fix native text mode initializationNick High
2016-04-29nb/intel/sandybridge/raminit: fix regression "always use mrccache"Patrick Rudolph
2016-04-10nb/intel/sandybridge/raminit: always use mrccachePatrick Rudolph
2016-04-05nb/intel/sandybridge/raminit: die in toplevel functionPatrick Rudolph
2016-04-05nb/intel/sandybridge/raminit: prepare raminit for fallbackPatrick Rudolph
2016-03-30nb/intel/sandybridge/raminit: move ram training into seperate functionPatrick Rudolph
2016-03-29nb/intel/sandybridge/raminit: move dimm_info into ramctr_timingPatrick Rudolph
2016-03-16cpu/x86/mtrr: move cache_ramstage() to its only userAaron Durbin
2016-03-13northbridge/intel/i3100: Unify UDELAY selectionStefan Reinauer
2016-03-13northbridge/intel/i82810: Unify UDELAY selectionStefan Reinauer
2016-03-12northbridge/intel/i82830: Unify UDELAY selectionStefan Reinauer
2016-03-11northbridge/intel: move mrccache.c of sandybridge + haswell to commonAlexander Couzens
2016-03-11northbridge/intel: move mrc_cache definition into a common headerAlexander Couzens
2016-03-11nortbridge/sandybridge/mrccache: parse the return code of flash->writeAlexander Couzens
2016-03-11northbridge/i945/gma: Re-enable NVRAM tft_brightnessAlexander Couzens
2016-03-10northbridge/intel/i440bx: Unify UDELAY selectionStefan Reinauer
2016-03-09northbridge/intel/gm45: Use TSC for ramstage timer per defaultStefan Reinauer
2016-03-05sandybridge/gma_lvds: support both Sandy&Ivy on one boardIru Cai
2016-03-03nb/intel/sandybridge/raminit: Fill SMBIOS type17 infoPatrick Rudolph
2016-03-02nb/intel/sandybridge/romstage: Read fuse bits for max MEM ClkPatrick Rudolph
2016-03-02nb/intel/sandybridge/raminit: Make discover_timC_write non cyclicPatrick Rudolph
2016-02-28northbridge/intel: add missing #include guardsIru Cai
2016-02-26nb/intel/sandybridge/raminit: Adjust timB to prevent overflowPatrick Rudolph
2016-02-26tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"Denis 'GNUtoo' Carikli
2016-02-20nb/intel/sandybridge/raminit: Add XMP supportPatrick Rudolph
2016-02-19nb/intel/sandybridge/raminit: Improve loggingPatrick Rudolph
2016-02-18nb/intel/sandybridge: Start PEG link trainingPatrick Rudolph
2016-02-18southbridge/intel/bd82x6x: Use common gpio.cPatrick Rudolph
2016-02-16nb/intel/sandybridge/raminit: Add shift offsetPatrick Rudolph
2016-02-13sandybridge: Always include MRC if not using native RAM init.Vladimir Serbinenko
2016-02-12Make MRC vs native a config rather than making a separate chipset for it.Vladimir Serbinenko
2016-02-12Merge sandy/ivybridge romstage flow for MRC and non-MRC.Vladimir Serbinenko
2016-02-10Kconfig: Move defaults for CBFS_SIZEMartin Roth
2016-02-09sandybridge: Set all native gfx-related options in northbridge code.Vladimir Serbinenko
2016-02-09ivy: Add a possiblity for mainboard early init.Vladimir Serbinenko
2016-02-09Revert "northbridge/intel/peg: Disable unused ports"Nico Huber
2016-02-04northbridge/intel/peg: Disable unused portsPatrick Rudolph
2016-02-04nb/intel/sandybridge/raminit: Fix two dimms per channelPatrick Rudolph
2016-01-29Revert "northbridge/intel/sandybridge: Fix random raminit failures"Vladimir Serbinenko
2016-01-29nb/intel/x4x: Move to early cbmemDamien Zammit
2016-01-29nb/intel/x4x: Cleanup gma.cDamien Zammit
2016-01-29nb/intel/x4x: Tidy up raminit and fix msbpos() functionDamien Zammit
2016-01-29nb/intel/x4x: Tidy up northbridgeDamien Zammit
2016-01-29nb/intel/x4x: Fix memory hole with both channels populatedDamien Zammit
2016-01-28nb/intel/pineview: Native VGA init (CRT)Damien Zammit
2016-01-26nb/intel/pineview: Increase MMCONF decoding to 256 bussesDamien Zammit
2016-01-20nb/intel/pineview: Use macro names for memory base registersDamien Zammit
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