summaryrefslogtreecommitdiff
path: root/src/northbridge/intel
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2016-06-18 21:08:58 +0200
committerPatrick Georgi <pgeorgi@google.com>2016-08-09 10:42:51 +0200
commit27f94eea6cf142a2bf92db96a6ae64cb380d78ca (patch)
tree87ddd5478307357e34937ba4f8c5f0bc468fe70e /src/northbridge/intel
parent5c4748b342fafb84dfaf03c3e8187b8e5bf9e3e9 (diff)
x4x: add non documented vram sizes
The Intel documtentation, "Intel ® 4 Series Chipset Family" mentions the possibility of 1, 4, 8 and 16M of preallocated memory for the IGD, but does not document this. This allows to set those undocumented values. TESTED on ga-g41m-es2l with 2G dimm in one slot and 2x2G. Change-Id: I92beb8d78907d4514a5aaf69248dd607dcf227c0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/15491 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/x4x/ram_calc.c2
-rw-r--r--src/northbridge/intel/x4x/raminit_ddr2.c3
2 files changed, 3 insertions, 2 deletions
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index 27562eae83..5a6a7675f1 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -28,7 +28,7 @@
/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
u32 decode_igd_memory_size(const u32 gms)
{
- static const u16 ggc2uma[] = { 0, 0, 0, 0, 0,
+ static const u16 ggc2uma[] = { 0, 1, 4, 8, 16,
32, 48, 64, 128, 256, 96, 160, 224, 352 };
if (gms > ARRAY_SIZE(ggc2uma))
diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index 5d457e6de1..ed6ab607e0 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -1625,7 +1625,8 @@ static void mmap_ddr2(struct sysinfo *s)
u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud;
u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit;
u16 ggc;
- u16 ggc2uma[] = { 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352 };
+ u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96,
+ 160, 224, 352 };
u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4};
ggc = pci_read_config16(PCI_DEV(0,0,0), 0x52);