diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2016-02-10 19:16:34 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-16 22:48:58 +0100 |
| commit | 0188b1399a9b8601ae03797c3e61ad7d382391ea (patch) | |
| tree | 4eaa38973891ad3dafb4ae944e6f61e3c9da83bb /src/northbridge/intel | |
| parent | 44ef167d21446cb8fcf52d337ea616a645c24707 (diff) | |
nb/intel/sandybridge/raminit: Add shift offset
It looks like the falling timing was missing the shift offset.
Not sure if this was intentional, I guess not.
Tested on my hardware and produced no regressions.
Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H
Please test on real hardware !
Change-Id: Id8c60217093a48bf322f406ea258c10a02c936e8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13682
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 7490ff7f29..54aa2e865c 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -1607,8 +1607,8 @@ static void program_timings(ramctr_timing * ctrl, int channel) (((ctrl->timings[channel][slotrank].lanes[lane]. timA + shift - (post_timA_min_high << 6)) & 0x1c0) << 10) - | (ctrl->timings[channel][slotrank].lanes[lane]. - falling << 20)); + | ((ctrl->timings[channel][slotrank].lanes[lane]. + falling + shift) << 20)); MCHBAR32(lane_registers[lane] + 0x20 + 0x100 * channel + 4 * slotrank) |