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Necessary to allow coolstar's Windows touchpad driver for this board,
since the touchpad is attached to the SMBus. The VID/DID combo used is
not registered/doesn't conflict with any currently in use, and would
be difficult to change at this point since the Windows drivers have
already been signed.
TEST=build/boot Win11, Linux on butterfly/lumpy/parrot, verify
touchpad driver works properly.
Change-Id: I61912fd6db9eb4b8d202ab633b8c7ca5913e759f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for redrix board. Please refer Intel doc#723158 for
more information.
BUG=b:292435264
TEST=build and boot redrix
Change-Id: I34d10c763f4710d2c5678704320fd1cc8d8b6287
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76670
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Camera LED will blink several times as sensor is being probed during
kernel boot.
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot and prevent privacy LED blink.
BUG=b:292173903
TEST=Build and boot on Yavilly EVT unit. Verify & observe Camera LED
blinking behavior.
Change-Id: Ic3e3439dc9313325189761b277e1a3bd1c1d9418
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76671
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These boards do not actually support RTD3. The power GPIOs for
components are connected to 3.3V and the reset GPIO is connected to
`PLT_RST#`.
Change-Id: Id5e318c388f669d6b2935dc98ae29485955e6e72
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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After switching to S3, it was found that drives on the SATA port do not
exit D3cold on S3 exit. Disable RTD3 on the port until the issue can be
resolved.
Avoids the following error in Linux:
pcieport 0000:00:1d.0: Unable to change power state from D3cold to D0, device inaccessible
Tested on darp8 with a Samsung 970 EVO or Crucial P5 in J_SSD1.
Change-Id: Ib26f59db61acfbf9248cea379c197765d3d9c470
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76593
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Lemur Pro 12 (lemp12) is a Raptor Lake-U board.
Tested with a custom edk2 UefiPayloadPkg.
Working:
- PS/2 keyboard
- I2C HID touchpad
- DIMM slot with 4800 MT/s memory
- Both SSD slots
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined 3.5mm headphone + mic audio
- 3.5mm microphone input
- S3 suspend/resume
- TPM 2.0 device
- Booting Pop!_OS Linux 22.04 with kernel 6.2.7
Not working:
- Onboard RAM
Change-Id: I0c4941534b719ea8fc93eb3492d5fe16db208647
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Bonobo Workstation 15 (bonw15) is a Raptor Lake-HX board.
Tested with a custom edk2 UefiPayloadPkg.
Working:
- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots with 5200 MT/s memory
- All M.2 SSD slots
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined 3.5mm headphone + mic audio
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.2.7
- TPM 2.0 device
Not working:
- Discrete/Hybrid graphics
- Thunderbolt
Change-Id: I6d4e408604a0c5c5272e841f4093baaf28c790cd
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add bank locator and slot existance to the mainboard code.
TEST: Verified on Linux that all slots show in dmidecode -t 17.
Change-Id: I4ced36e26368d3f99a7341cb55a8deb118b2d1a4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The SuperIO is not used so don't enable decoding of 0xE2 and
drop all code using it. It's not even required for the virtual
UART on 0x3f8 to work.
Add the virtual UART on 0x3f8 as ACPI device.
TEST: Verified on SBP1 that serial still works.
Change-Id: I8e431a0c8417435cc6e3ba16f97ff080e1656a7b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Add pujjo new supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Hynix H58G56BK7BX068
2. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT
3. Micron MT62F1G32D2DS-026 WT:B
BUG=b:292452868
TEST=Use part_id_gen to generate related settings
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ia123a1cfd93a5e08ab0ba65f1d9be240d60ff356
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76672
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch creates a new variant screebo4es.
The new variant will support only ESx samples. The existing rex
variant will support the QS samples.
BUG=b:292280656
TEST=Able to build google/screebo4es board and boot on target
hardware.
Change-Id: If77b4a773bee3633008d39c1886b61869c9618de
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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BUG=b:290894460
TEST=`emerge-rex coreboot chromeos-bootimage`
then check variant name with image*.bin.
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I8f739485dbaab074f57eaa4dacc9f228a3f4aa14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76667
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable the APOB cache for only Myst, and re-enable APOB for other
Phoenix SOC mainboards.
BUG=b:290763369
TEST=verify APOB cache is disabled
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ie611e0b84611b2f50c989c75612fc2186b2dbfdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76567
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Mapping to the fw_config of AUDIO_AMP in dedede,
and set new AUDIO_AMP configuration of ALC5650 as value 4.
BUG=b:284060672
BRANCH=dedede
TEST=build pass
Change-Id: Ic3dccd09d3ba1619cce2ac0d5f123badbeeaccdc
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch increases the `tcc_offset` to reduce the TCC
(Thermal Control Circuit) activation temperature to avoid running
into abrupt power off during power cycle tests.
On Intel processors, the core frequency can be by an HW agent when
the current temperature reaches the TCC activation temperature.
The default TCC activation temperature is specified by MSR_IA32_TEMPERATURE_TARGET (which is 90°C for google/rex variants).
However, this patch adjusted the TCC by specifying an offset in
degrees C (i.e., using `tcc_offset` from variant override device tree).
Note: The bigger the TCC offset is, the lower the effective TCC activation temperature would be, to ensure that processors can be throttled earlier before the system critical overheats.
BUG=b:283008762
TEST=Able to perform power cycle on google/screebo w/o any crash/shutdown.
Change-Id: Ib19703877dbbfc26b2d9f538dda4f10c27cf872d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76658
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the
Kernel when an EC panic occurs. If system safe mode is also enabled
on the EC, the kernel will have a short period to extract and save info
about the EC panic.
BUG=b:290985698
BRANCH=firmware-volteer-13672.B
TEST=Observe kernel ec panic handler run when ec panics
Change-Id: I87173f93d0e47baa816d15dad0777007342b4fdb
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Choose BOARD_GOOGLE_MODEL_REX while setting up the default config value
for variants created using google/rex model.
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I107f4e375b5c9e9c0fb80c4d396164c10c1fc1e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch creates a new variant rex4es. The new variant will support ESx samples. The existing rex variant will support the QS samples.
BUG=b:290732344
TEST=Able to build google/rex4es board and boot on target hardware.
Change-Id: I25dd1f42ee812f47289da0c2ef7aa79d6f340d48
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch creates a rex model so that other variants developed using
`rex` baseboard are easy to land without duplicating the config
selection.
So far, `rex0` and `rex_ec_ish` are developed using the `rex` model.
The plan is to extend the support for `rex4es` and `rex4es_ec_ish`
variants.
TEST=Able to build and boot google/rex.
Change-Id: Id4e8d1162da93b7266ee1108f870e89b6d884ab9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76608
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Follow baseboard Rex to make GPIO changes
BUG=b:286187821
TEST=Ability to enable and disable WIFI function in OS.
Change-Id: I805ce859c42c7c0a9d117418a80555658f844e09
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76551
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
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This supports a brand new I2C driver that is designed specifically
for the Pixel 2013 chromebook (LINK). The GMBus interface on the IGPU
is an i2c-compatible interface, but AFAIK only Link has touch devices
attached in this way.
On Windows, the PCIe device for the IGP is owned by the Intel
proprietary driver, hence a separate ACPI device has to be added for
the I2C driver arbitrator to attach to. The MMIO method is used instead
of _CRS so that Windows does not try to assign ownership of the
resource to our device (even though we're using the MMIO registers at
the same time as the IGP driver).
Even though in theory 2 drivers accessing the same MMIO may cause
problems, in testing, there has been no issues with
sleep/wake/hibernate, updating/installing/uninstalling the IGP driver,
or changing display resolutions with the i2c driver attached.
The arbitrator is necessary as well, since even though there are
multiple i2c buses, the MMIO registers are shared. Hence a shared lock
is required for i2c access across the buses.
The original Sleep Button devices are preserved for Linux due to the
completely custom and non-standard implementation of the Windows driver
in order to work around the non-standard nature of Link's hardware.
Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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CPU:
- 2 SPR sockets
- 64 total PCIe 5.0 lanes with up to 64 lanes of Flex Bus/CXL per CPU
- Up to 32 DDR5 DIMM
- 1 Gbase-T NIC port
- 1 USB3.0 type A, 1 USB2.0 connector
- 1 VGA connector
BMC:
- ASPEED AST2600 BMC
- 1 DDR4 8Gb memory
- 1 8GB eMMC
Test:
The board boots to Linux 4.19.6 with all 192 cores available.
Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684
Signed-off-by: Annie Chen <Chen.AnnieET@inventec.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Wei Chen <Chen.HW@inventec.com>
Reviewed-by: Annie Chen <chen.annieet@inventec.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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In order to reduce S0ix resume time, decrease stop_delay_ms from
300ms to 200ms for Goodix GT7996F. The value source is from
https://partnerissuetracker.corp.google.com/issues/285999032#comment16.
BUG=b:285999032
BRANCH=firmware-nissa-15217.B
TEST=boot uldren to ChromeOS and touchscreen is workable.
Change-Id: I2f0adadbd3d0774da03338cc0abd1639104876d9
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76577
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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There is a problem of screen shake on the old panel[1]. So increase the
panel GOP component pull-down circuit size in hardware, and update the
initialization code at the same time. The new initialization code is
mainly adjusted for GOP timing. When Display sleep in, raise all GOP
signals to VGHO and then drop to GND. In order to be consistent with
the current panel model, let's rename this file.
[1]: INX old panel product number is HJ110IZ-01A-B1, and the new
panel product number is HJ110IZ-01A-B2. We have recalled the shipment
old panel.
BUG=b:270276344
BRANCH=trogdor
TEST= test firmware display pass
Change-Id: I2b2534afee1ed700c39d3c360aafd685b63ccbfb
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This patch updates the Type-C USB2/3 port mapping to reflect the mux
connection change as mentioned in previous patch
commit ee3f796200bf3baf8a1906 (mb/google/rex/var/ovis: Fix mux
change as per schematics).
Here is the correct port mapping after considering the mux swap:
+--------------------------------+-------------+---------------+
| TCSS-USB Mapping | Port C0 | Port C1 | Port C2 |
+------------------+-------------+-------------+---------------+
| USB2-Port | 2 | 3 | 1 |
| USB3-Port | 0 | 2 | 1 |
+------------------+-------------+-------------+---------------+
BUG=b:289300284
TEST=Able to build and boot google/ovis to get display over Type-C1
and Type-C2 port.
Change-Id: I460004842dd8fcdc03fca6639d03e422259380ca
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76464
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change SD_CLKREQ_ODL from GPP_D19 to GPP_D18
BUG=b:291051683
BRANCH=none
TEST=emerge-rex coreboot
Change-Id: Ic102e42482328580c5334e6ff036b774f5002e00
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76565
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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According to Intel doc#763797 to overcome early command training hang
issue, the CsPiStartHighinEct needs to be enabled for hynix memory.
BUG=b:284192689
BRANCH=firmware-brya-14505.B
TEST=Built and booted into OS.
Change-Id: Ic177c5ffcb6a3d3f76292a0d99ab0e806d43fc11
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76549
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Enable CsPiStartHighinEct to fix MRC Cache fail issue
BUG=b:279835630
BRANCH=none
TEST=Pass MRC Cache test with toolkit 1000 times
Change-Id: I25cd856785bab9c661e30e2987b43f0dc2ba9564
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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According to Intel doc#763797 to overcome early command training hang
issue, the CsPiStartHighinEct needs to be enabled for hynix memory.
BUG=b:281643325
BRANCH=firmware-brya-14505.B
TEST=Built and booted into OS.
Change-Id: I95702e675fa3b73c7e8ee0c8625c7828d8129ea8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76355
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Galago Pro 7 (galp7) is a Raptor Lake-H board.
Tested with a custom TianoCore UefiPayloadPkg.
Working:
- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots (with NMSO480E82-3200EA00)
- M.2 NVMe SSD
- All USB ports
- SD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Backlight controls on Windows 10 and Linux 6.2
- HDMI output
- DisplayPort output over USB-C
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.2.7
Not working:
- Detection of devices in TBT slot on boot
Change-Id: I1ae3b2c647aa75976a1ea97f7681f93eb000ba8a
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75277
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable the CSME by default now that S3 is used instead of S0ix.
The CSME will not go into a low power state during S0ix when it is
disabled. This prevents the CPU from reaching C10 and so increases the
power usage during suspend compared to leaving CSME enabled. (This was
measured to be a ~2W different on TGL-U.) In S3, the state of the CSME
doesn't matter because the CPU will be off.
Change-Id: I88c0aebdcc977f3ba9dd8f46a6abfaa7a4ae8eb6
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73354
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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System76 EC since system76/ec@9ac513128ad9 detects if the keyboard is
white or RGB backlit via `RGBKB-DET#` at runtime. Remove the Kconfig for
the selection and update the ACPI methods for the new functionality.
Change-Id: I60d3d165a58e30d2afc8736c0eb64dd90c8227ca
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76152
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Darter Pro 9 (darp9) is a Raptor Lake-P board.
Tested with a custom TianoCore UefiPayloadPkg.
Working:
- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots with 5200 MT/s memory
- Both M.2 SSD slots
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined 3.5mm headphone + mic audio
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.2.7
Change-Id: If19caa90e5f90939b2946392da343b7f91f568ca
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75278
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
The Serval Workstation 13 (serw13) is a Raptor Lake-HX board.
Tested with a custom TianoCore UefiPayloadPkg.
Working:
- PS/2 Keyboard
- I2C HID touchpad
- Both DIMM slots with 5200 MT/s memory
- Both M.2 SSD slots
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined 3.5mm headphone + mic audio output
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.2.7
Not working:
- Discrete/Hybrid graphics
- Thunderbolt
Change-Id: Id709a7d06854ba9de673d5e3f25c0a1bbcc53d21
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73440
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
After fixing TPM logs clobbering other regions in CB:73297, S3 no longer
causes cache issues resulting in power off after multiple suspends.
This is required for disabling Intel CSME by default.
Change-Id: I7eef4c883fd65db93dae81adabd895b2de90496a
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:290876132
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Change-Id: Id5e0ba7a4ca57e311465ba8e74105f5ee7b8ee8a
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76435
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use fw_config to separate pujjoteen5 intel wifi sar table.
BUG=b:279984381
Test=emerge-nissa coreboot
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I2e744bf0801bd7b18817a00fcbe3d0c62b8fc3d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76453
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Add an initial overridetree for gothrax based on the schematic.
BUG=b:274707912
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: Idfd9788a75f9c342f85d6e1a3d54327d64797dd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76013
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Drivers for Pen Garage/SDCard Reader/LTE/SAR/WWAN and I2C for TPM.
BUG=b:274707912
BRANCH=None
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I1203ca13bd55b8ab96ce5d323a36ffde06860fa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76104
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
|
|
Change-Id: I5c5b125ac03e07a22bcc15ad2d34c62edf74ee04
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76452
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change i2c[0] parameter Thd:dat = 50ns;
Change i2c[1] parameter Thd:dat = 100ns;
BUG=b:287898252
BRANCH=none
TEST=Test success by EE.
Change-Id: Ibdbe4e17cf21c914b48fa6dc7d3eecf8218a2d8b
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76430
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch disables early EC sync to avoid an idle delay (~3sec)
without a provision to notify the user about some critical task
in progress.
Doing EC sync at later stage allows us to notify using graphical msg
on screen to make user aware of the WIP task.
BUG=b:279944831
TEST=Able to perform EC sync from depthcharge on google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I03ed40827c50e75ceaaf94e30d675014ebf22dac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
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Disable DMI link ASPM which can degrade performance of overall system.
Desktop does not need to be concerned that much about idle power
consumption.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I60af9d2ab2913db449059e1e007999fa2f307f5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69826
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Change touchscreen reset_gpio GPP_C01 -> GPP_D07;
Change touchscreen enable_gpio GPP_C00 -> GPP_B17.
BUG=b:289425753
BRANCH=none
TEST=Test success by EE.
Change-Id: I7be6a2b4e87126b281f138c819d2a0a5b1af5821
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Create the craaskov variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:290248526
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_CRAASKOV
Change-Id: I1d12f7c3d0ef7067f4530c1c69c560f9a83561f6
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
|
|
Add karis supported memory parts in mem_parts_used.txt, generate
SPD id.
1. MICRON MT62F1G32D2DS-023 WT:B
2. HYNIX H9JCNNNBK3MLYR-N6E
3. HYNIX H58G56BK8BX068
4. SAMSUNG K3KL8L80CM-MGCT
BUG=b:291018417
TEST=Use part_id_gen to generate related settings
Change-Id: I87c2c4f59454dec84d29590ee91379c9fa60ddcf
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76443
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Iad0244e798c03a26f755024453ecdd745e6286f3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76473
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Iafc3735b6d903a4496828189db14b09d3c4d2081
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76432
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The PRESERVE flag in the FMD file tells futility not to erase the
fmap partition when updating the firmware. Because of an issue on
myst right now, we want the RW_MRC_CACHE partition to be erased
when the firmware is updated.
BUG=b:290763369
TEST=None
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id586ae057b2fd6d513ddbba5e1284dea39467d95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76478
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
System76 boards use the VBT data file, not the VGA optionrom.
Change-Id: Ie4100e09221ae4f301a621e7aac62e38ac04a444
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
|
|
Use the proper dxio_link_hotplug_type enum values for the link_hotplug
field in the DXIO descriptors to replace the magic values in the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieb1513737e6022a668287dc80a39d96cda2b18d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76439
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change `CBFS_SIZE` to match the actual BIOS region size, as specified in
the FIT XML config.
Fixes building with `VALIDATE_INTEL_DESCRIPTOR` selected.
Change-Id: I91a46b3ed6cc3161df27eed19d8cdf2820e90d7e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76326
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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It moves cr50_plat_irq_status() to common code and adds Kconfig
option to specify GPIO used for interrupt.
BUG=b:277787305
TEST=Build all affected platform and confirm using right GPIO
number. Tested on Skyrim.
Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8
Signed-off-by: Grzegorz Bernacki <bernacki@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75621
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
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The Adder Workstation 3 (addw3) is a Raptor Lake-HX board.
Tested with a custom TianoCore UefiPayloadPkg.
Working:
- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots with 5200 MT/s memory
- Both M.2 SSD slots
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.2.7
Not working:
- Discrete/Hybrid graphics
- Thunderbolt
Change-Id: I165a434fe18f8c0aac49cb872bb87f98551d8f2c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked
for CNVi.
Meteor Lake rex platform does not wake up from low power state by
bluetooth keyboard and mouse properly. It is identified that IO Standby
State needs to be configured as masked to function properly for CNVi.
BUG=b:286803481
TEST=Make screebo suspend to s0ix state and press a key from
bluetooth keyboard. Check the platform wakes up properly from s0ix.
Change-Id: I7fd342e52fa0f9126eab4c857a5adc04c26e49c6
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76406
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Pujjo support WWAN EM060 device, use FW_CONFIG to handle the
power on sequence.
BUG=b:290709711
TEST=Build and check WWAN EM060 power on sequence.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I66800c75274e8e1e55d4314c82b7fcdf2a4477bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76403
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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With the latest hardware revision, the polarity of GPP_B5 has been
changed. For a full-populated DRAM configuration, the input signal is
now connected to 3.3 V and for a half-populated configuration it is
connected to ground.
BUG=none
TEST=Use different populated mainboards and check coreboot log
GPP_B5 = 0:
[INFO ] meminit_channels: DRAM half-populated
[DEBUG] 1 DIMMs found
GPP_B5 = 1:
[DEBUG] 2 DIMMs found
Change-Id: Iaa3a63fa52c802d8f5d8c6cc11dd6edfac117e88
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76434
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Modify reset_delay_ms from 300ms to 6ms for ELAN EKTH7D18.
BUG=b:285999032
BRANCH=firmware-nissa-15217.B
TEST=boot uldren to ChromeOS and touchscreen is workable.
Change-Id: Iffcddbe7735b7a837887dec68e1270c2af5f4556
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76417
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Avoid enabling SIO UART to prevent conflicts with BMC console; utilize VUART0 instead.
TEST=Build for sbp1 & make sure coreboot logs do not spill into BMC
console. Also made sure coreboot logs are accessible via VUART.
Change-Id: I2d4bbd74bb7d37b74378650dd569bca7fa13c29b
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76396
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
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Set coreboot ready gpio. This gpio is used to indicate to BMC of BIOS
completion.
Change-Id: Iaed8bec12e593cf1687d973765b0117bdc115cb8
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76404
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch enables PCH to CPU energy report feature which can be used
by Intel Telemetry Driver.
BUG=b:269563588
TEST=Able to build and boot google/rex and perform below check to ensure
the energy reporting is correct
w/o this cl:
# lspci -s 00:14.2 -vvv | grep "Region 0"
Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K]
# iotools mmio_read32 0x957f8068 #i.e., 104th offset
0xXXXX0000
w/ this cl:
#lspci -s 00:14.2 -vvv | grep "Region 0"
Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K]
# iotools mmio_read32 0x957f8068 #i.e., 104th offset
0xXXXXfc004
Change-Id: I9bd4625ea311a05071878aaec68433a1ba018c0d
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76353
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
|
CPUID is the same for Alder Lake and Raptor Lake S and HX variants.
To reduce the confusion and concerns how to name the macros, remove
the suffixes from macros and platform reporting strings. Thankfully
the stepping names are unique across mobile (P suffixed) and desktop
(S and HX suffixed) SKUs. Distinguishing the S from HX is possible via
host bridge PCI ID.
Change-Id: Ib08fb0923481541dd6f358cf60da44d90bd75ae2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
|
|
The CB:76219 removed mtk_i2c_bus_init() from tps65132s_setup(), so
we should initialize I2C bus for TPS65132 in mainboard now.
BUG=None
TEST=./util/abuild/abuild -t google/geralt -a
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: Iacf78221d2416f41467c709402b7e02e03dc5fc7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Idd623e99ee20ad94e493c8560cfdac9f7baaf890
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76281
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There is no PCH FIVR participant on MTL and we should remove it
in Rex.
TEST=compile ok and make sure there no TPCH device in acpi
BUG=b:290322310
Change-Id: Icf4be86da3f3cb9b1f0a3f2586b029a533c3e6a9
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76402
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
for saving boot time, change ramstage compression from LZMA to LZ4.
Boot time saving is around 35ms (30-37ms) while SPI size impact is 230KB.
For detail, refer below.
Existing: LZMA(55.6 ms)
8:starting to load ramstage 894,519 (0)
15:starting LZMA decompress (ignore for x86) 903,556 (9,036)
16:finished LZMA decompress (ignore for x86) 949,997 (46,441)
9:finished loading ramstage 950,179 (182)
Changed: LZ4(17.8ms)
8:starting to load ramstage 900,876 (0)
17:starting LZ4 decompress (ignore for x86) 917,650 (16,774)
18:finished LZ4 decompress (ignore for x86) 918,690 (1,040)
9:finished loading ramstage 918,849 (158)
Size impact (73KB * 3 = 219KB)
fallback/ramstage 0x62940 stage 240281 LZ4 (405524 decompressed)
fallback/ramstage 0x62940 stage 165452 LZMA (405524 decompressed)
BUG=b:286930648
TEST= Boot to OS and check boot time
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked
for CNVi to function properly with the connected bluetooth devices and
wake up from low power state.
BUG=None
TEST=None
Change-Id: I977493fd95a99381279f5a3f5e679e4893369b8a
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
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This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked
for CNVi.
Meteor Lake rex platform does not wake up from low power state by
bluetooth keyboard and mouse properly. It is identified that IO Standby
State needs to be configured as masked to function properly for CNVi.
BUG=None
TEST=Make rex platform suspend to s0ix state and press a key from
bluetooth keyboard. Check the platform wakes up properly from s0ix.
Change-Id: Ia98abde584699fa01acba47a9df4ef6332ac16fd
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76338
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The actual NVM size of camera module is 64KB; however, only 8KB is in
use to store data. This reduces the size of both NVM0 and NVM1 to 8KB
to minimize the time taken to read NVM and launch Camera preview.
BUG=NONE
TEST=Launch Chrome camera application and check the time taken to
read eeprom from camera service log and show camera preview. It takes
2 to 3 seconds to show camera preview while it takes 4 to 5 seconds
without the changes.
Before the changes:
06:21:04.204944Z OpenDevice(): camera_id = 1
06:21:07.297584Z Read camera eeprom from eeprom
06:21:08.763491Z Read camera eeprom from nvmem
After the changes:
21:37:23.923676Z OpenDevice(): camera_id = 1
21:37:24.386020Z Read camera eeprom from eeprom
21:37:24.574515Z Read camera eeprom from nvmem
Change-Id: I0e2272b3307fea60ea7406fc6899ae2cb0134fa3
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76189
Reviewed-by: Kiran2 Kumar <kiran2.kumar@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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Update eMMC DLL tuning values for improved initialization reliability
BUG=b:289763421
TEST=cold reboot stress test over 5000 cycles on Foresee and Kingston
eMMC
Change-Id: I63077b8717feecf3d50507abb188b7fadb5d6c79
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76221
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This patch skips reading the MEM_CH_SEL GPIO aka GPP_E13 to determine
the memory channel configuration. The signal behavior is not proper,
hence limiting the DIMM capacity to half (only MC0 is enabled).
This patch always reports the full memory capacity as in dual channel
(both MC0 and MC1 enabled).
This change is necessary to ensure that the system reports the correct
memory capacity, even if the MEM_CH_SEL GPIO is not working properly.
BUG=b:290174538
TEST=Able to detect 32GB memory capacity while booting google/ovis.
Without this patch:
localhost ~ # cat /proc/meminfo
MemTotal: 16183080 kB
With this patch:
localhost ~ # cat /proc/meminfo
MemTotal: 32673664 kB
Change-Id: I6c3fa941abb044b79b13785f7b65d09957f0487d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76359
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Since multiple GFX entry causes an ACPI error when trying to write _DOD
method multiple times, combine the GFX entry into one so that _DOD
method is written just once.
BUG=b:289854155
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I22ad70d50f1aecf8da70e8dd04a36a0a7c1c7609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76329
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This CL corrects the trigger for HID over SPI from Level to Edge.
BUG:None
TEST:Tested with I2C and SPI
Change-Id: I78937af22df22d80a702477b6790a7aa40d782a4
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76116
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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The AW37503 is designed to supply positive/negative supply for driving
the MIPI panel. It doesn't integrate non-volatile memory(EEPROM), so we
need to program the registers at boot. We program the target
positive/negative output voltage via I2C and enable the power rails by
pulling up ENP and ENN pins.
On Starmie, we need +/-6V power supply for the MIPI panel. We program
the AW37503 registers in coreboot so that kernel can control AW37503
via fixed regulators without additional settings(what we did for
TPS65132). Since we distinguish AW37503 and TPS65132 by reading the
vendor ID, we need to initialize I2C bus as early as possible.
Therefore, we move mtk_i2c_bus_init() to mainboard_init().
BUG=b:289482828
TEST=emerge-staryu coreboot chromeos-bootimage
TEST=Test the sequence the voltage
Change-Id: I9ccd4db19c93a032226f006eab0427f78f7b6dc8
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76219
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a new kingler follower 'ponyta'.
BUG=b:290259648
TEST=make # select ponyta
Signed-off-by: cengjianeng <cengjianeng@huaqin.corp-partner.google.com>
Change-Id: I74759441957e9901bd7e5a709a2ae7d97a7cd040
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76331
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
|
|
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ia756f842943b8e1f1877db7433641e6bbd05f45b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74407
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I889db739d6e006c1753eb8c0d208cf471d09f18d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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The BT VGPIOs pad config in variant of gpio.c won't be overwritten on board eventually because no matched gpios existed here.
Put BT VGPIOs in gpio_table, ensure that these were able to be overwritten.
The fix included crota and omnigul BT offload work successfully.
BUG=b:264834572
TEST=test Bluetooth offload playback/capture in SCO profile.
Change-Id: I62cecf26abd0411f7cbb0a56b8b8f0a25d370c69
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Add fw_config and configurate AUX pin for MB USB Type-C.
MB USB3 doesn't have re-timer, thus have to configurate the AUX pin.
BUG=b:275335023
TEST=build pass
Change-Id: I1334dcbaec6de1707c6892efbebaf8d460ba8648
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76348
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
|
|
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100
MHz for starting next phase.
BUG=b:270500631
BRANCH=None
TEST=emerge-skyrim coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I0915d9b10dbfae7fff4e8874011951d1690de870
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
|
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constitution only has one TBT port, remove tcss_dma1.
BUG=None
TEST=emerge-constitution coreboot
Change-Id: Ia4eb4371eb20e75a0f464e2b087fd2fe59569537
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Pablo Ceballos <pceballos@google.com>
|
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Add a new apcb edit tool, apcb_v3a_edit.py, that injects SPDs into
an APCB for phoenix platform.
The tool makes several assumptions:
* Each SPD only uses blocks 0, 1, 3 and 5. All other blocks are zero.
* Each block is 64 bytes.
* Dimm and socket are always 0
* Unused SPD entries are zero'd
BUG=b:281983434
BRANCH=None
TEST=build, flash, boot myst
Change-Id: Ifb50287de77138170714a702ab87d56427aacfef
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76188
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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tis_plat_irq_status() function is used only by Google TPM. It should
be moved to drivers/tpm/cr50.c. The name of the function was changed
to cr50_plat_irq_status().
BUG=b:277787305
TEST=Build all affected platforms
Change-Id: I78dc39f2c7b44232b06947d3dfe6afa52807ced8
Signed-off-by: Grzegorz Bernacki <bernacki@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75917
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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Always exit 4-byte addressing mode to prevent errors when the spi flash
is not left in 4-byte addressing mode.
TEST=boot with PSP releases that leave the flash in both 4-byte
and 3-byte mode and verify flash writes
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9884b85bc3b0a9b654a2cb91fb314b0869abd622
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76094
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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GPIO GPP_B5 is used as input on this mainboard. For a full-populated
DRAM configuration, the input signal is connected to ground and for a
half-populated configuration it is connected to 3.3 V.
BUG=none
TEST=Use different HW configurations and check coreboot log
GPP_B5 = 0:
[DEBUG] 2 DIMMs found
GPP_B5 = 1:
[INFO ] meminit_channels: DRAM half-populated
[DEBUG] 1 DIMMs found
Change-Id: I48b4a3bea7f1ff804b78b7c648a7ea1925627b8a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76245
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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There can be mainboard variants, which are only equipped with
half-populated DRAM. For this reason, the meminit parameter for
populatation should be adjustable. The default setting remains at
full-populated DRAM. At mainboard variant level a different selection
via individual input paths can be made.
Change-Id: I390bbfa680b5505bb2230fa0740720bd9dd1fafb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76244
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Align implementation with real hardwares, such that ECAM
(PCI configuration via MMIO) is available for use when
console is initialised.
Change-Id: I288991f31d3f1678132aa4315168c09eabbbe98d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76206
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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This devices is always present so hooking up the ops in devicetree makes
more sense.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I369129e365ce8596cad25b97d12168bb08e3ed0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76241
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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None of these boards have an RTC battery, so this option has no
effect. Remove it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9a55227f74c0b9ae9b56bdef4b8f53b2425b331c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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It is not needed, so remove it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I606d0a76926e90e4ce321163400aa50ea961c2a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75342
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
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Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. K4U6E3S4AB-MGCL (Samsung)
2. K4UBE3D4AB-MGCL (Samsung)
BUG=b:289873670
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I7a262ac62c24cfb43c0283c9730c177a242342e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76240
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
VP2420 (vault_ehl) has only 1 DIMM slot present. Set the DIMM_MAX to 1
to optimize the common libraries to not attempt to read and parse more
SPD than needed.
TEST=Boot Protectli VP2420 (vault_ehl) with different DIMMs and see
FSP is retraining the memory properly and fastboot is working.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I29a99f387ffe2df1060547e0818c5c5b66a27061
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73819
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Set tcc_offset value to 20 in chipset for Thermal Control
Circuit (TCC) activation feature for meteorlake silicon.
Also, remove tcc_offset default value from rex baseboard
and variants.
BUG=b:270664854
BRANCH=None
TEST=Build FW and test on rex board
Change-Id: Ieec1b7e0873eef46a56e612ed1d9445019b1f4a9
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Change i2c[3] parameter to meet below timing:
t-HIGH > 600ns;
900ns > Thd:dat > 300ns.
BUG=b:286030723
BRANCH=none
TEST=Test success by EE.
Change-Id: I4b2d958a5a0d41e2cfa1087f5cb94cc83bbb1739
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76169
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Set tcc_offset value to 10 in devicetree for Thermal Control
Circuit (TCC) activation feature for ovis.
BUG=b:270664854
TEST=Build and boot google/ovis.
Change-Id: I0ef626f6cc460f1b460297804b97038705efaf4c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch adds a power limit for Ovis with 28W Intel Meteor Lake
silicon.
Reference: Intel MTL-UH_Power_Map_Rev1p2, doc: 640982
BUG=b:289854108
TEST=Able to boot google/ovis with power limit being overridden as
appropriate to 28W.
Change-Id: I312c70720fd89261c53d5bd4f45236e829d6c790
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Currently, boards with ES2 silicon are unable to boot with crashlog
enabled because crashlog driver is unable to handle invalid data.
Temporarily disable the crashlog to unblock development until the issue
is fixed.
BUG=b:289749310
TEST=Able to boot to the OS on Screebo
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ic63cf9cf5bfa2c92d8f2c5b13df2f23dc118b389
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76231
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
|
|
Change i2c[0] parameter to meet touchscreen timing.
Thd:dat > 100ns.
BUG=b:287898252
BRANCH=none
TEST=Test success by EE.
Change-Id: I30e7c87d788f7f144276c45e8475af65f1f132ae
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch enables BT offload feature for soundwire audio over SSP1.
BT mode is selected via FW_CONFIG and corresponding VGPIOs are
programmed.
BUG=b:275538390
TEST=build and verify BT offload on rex soundwire audio
Change-Id: I99df78787d9f54c91bcedf6f70352890a715cdb3
Signed-off-by: Uday M Bhat <uday.m.bhat@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75924
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Follow the Project_Uldren_Thermal_paramters_list_2023_0626.xlsx to
modify DPTF parameters and tcc_offset.
- Set tcc_offset to 3.
- Update Critical Policy trip point.
- Update Power Limits PL1 minimum step size to control limits (in mW).
BUG=b:282598257
BRANCH=firmware-nissa-15217.B
TEST=boot uldren to ChromeOS and pass thermal test.
Change-Id: Ic5bbb3aa3b036a1eae8a95f63b570db2dc6da978
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76105
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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