mb/inventec: Add Intel SPR server board Inventec Transformers

CPU:
- 2 SPR sockets
- 64 total PCIe 5.0 lanes with up to 64 lanes of Flex Bus/CXL per CPU
- Up to 32 DDR5 DIMM
- 1 Gbase-T NIC port
- 1 USB3.0 type A, 1 USB2.0 connector
- 1 VGA connector

BMC:
- ASPEED AST2600 BMC
- 1 DDR4 8Gb memory
- 1 8GB eMMC

Test:
The board boots to Linux 4.19.6 with all 192 cores available.

Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684
Signed-off-by: Annie Chen <Chen.AnnieET@inventec.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Wei Chen <Chen.HW@inventec.com>
Reviewed-by: Annie Chen <chen.annieet@inventec.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

18 files changed, 916 insertions, 0 deletions

diff --git a/src/mainboard/inventec/Kconfig b/src/mainboard/inventec/Kconfig
new file mode 100644
index 0000000000..24c57292bf
--- /dev/null
+++ b/src/mainboard/inventec/Kconfig
@@ -0,0 +1,15 @@
+if VENDOR_INVENTEC
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/inventec/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/inventec/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	default "Inventec"
+
+endif # VENDOR_INVENTEC
diff --git a/src/mainboard/inventec/Kconfig.name b/src/mainboard/inventec/Kconfig.name
new file mode 100644
index 0000000000..c4b0c355b7
--- /dev/null
+++ b/src/mainboard/inventec/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_INVENTEC
+	bool "Inventec"
diff --git a/src/mainboard/inventec/transformers/Kconfig b/src/mainboard/inventec/transformers/Kconfig
new file mode 100644
index 0000000000..dff7c4e1f0
--- /dev/null
+++ b/src/mainboard/inventec/transformers/Kconfig
@@ -0,0 +1,38 @@
+if BOARD_INVENTEC_TRANSFORMERS
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_65536
+	select CONSOLE_OVERRIDE_LOGLEVEL
+	select IPMI_OCP
+	select IPMI_KCS
+	select IPMI_KCS_ROMSTAGE
+	select MEMORY_MAPPED_TPM
+	select MAINBOARD_HAS_TPM2
+	select MAINBOARD_USES_FSP2_0
+	select SOC_INTEL_SAPPHIRERAPIDS_SP
+	select SUPERIO_ASPEED_AST2400
+	select HAVE_ACPI_TABLES
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select VPD
+	select OCP_VPD
+	select OCP_EWL
+	select SOC_INTEL_XEON_RAS
+	select RUNTIME_CONFIGURABLE_SMM_LOGLEVEL
+
+config MAINBOARD_DIR
+	default "inventec/transformers"
+
+config MAINBOARD_PART_NUMBER
+	default "Transformers"
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+config MAX_SOCKET
+	default 2
+
+config DEBUG_SMI
+	default y
+
+endif
diff --git a/src/mainboard/inventec/transformers/Kconfig.name b/src/mainboard/inventec/transformers/Kconfig.name
new file mode 100644
index 0000000000..337156fa9e
--- /dev/null
+++ b/src/mainboard/inventec/transformers/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_INVENTEC_TRANSFORMERS
+	bool "Transformers"
diff --git a/src/mainboard/inventec/transformers/Makefile.inc b/src/mainboard/inventec/transformers/Makefile.inc
new file mode 100644
index 0000000000..7619419f67
--- /dev/null
+++ b/src/mainboard/inventec/transformers/Makefile.inc
@@ -0,0 +1,4 @@
+bootblock-y += bootblock.c
+romstage-y += romstage.c
+romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi.c
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
diff --git a/src/mainboard/inventec/transformers/acpi/platform.asl b/src/mainboard/inventec/transformers/acpi/platform.asl
new file mode 100644
index 0000000000..f2724daa46
--- /dev/null
+++ b/src/mainboard/inventec/transformers/acpi/platform.asl
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+/* The APM port can be used for generating software SMIs */
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+OperationRegion (DBG0, SystemIO, 0x80, 0x02)
+Field (DBG0, ByteAcc, Lock, Preserve)
+{
+	IO80, 8,
+	IO81, 8
+}
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method (_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method (_WAK, 1)
+{
+	Return (Package (){ 0, 0 })
+}
diff --git a/src/mainboard/inventec/transformers/board.fmd b/src/mainboard/inventec/transformers/board.fmd
new file mode 100644
index 0000000000..92831e7742
--- /dev/null
+++ b/src/mainboard/inventec/transformers/board.fmd
@@ -0,0 +1,13 @@
+FLASH 64M {
+	SI_ALL@0x0 0x03000000 {
+		SI_DESC@0x0 0x1000
+		SI_GBE@0x1000 0x2000
+		SI_ME@0x3000 0x2fed000
+		SI_PT@0x2ff0000 0x10000
+	}
+	RW_MRC_CACHE@0x3000000 0x10000
+	FMAP 0x800
+	RW_VPD(PRESERVE) 0x4000
+	RO_VPD(PRESERVE) 0x4000
+	COREBOOT(CBFS)
+}
diff --git a/src/mainboard/inventec/transformers/board_info.txt b/src/mainboard/inventec/transformers/board_info.txt
new file mode 100644
index 0000000000..2746ed2198
--- /dev/null
+++ b/src/mainboard/inventec/transformers/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Inventec
+Board name: Transformers
+Category: eval
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/inventec/transformers/bootblock.c b/src/mainboard/inventec/transformers/bootblock.c
new file mode 100644
index 0000000000..b781b6b0e3
--- /dev/null
+++ b/src/mainboard/inventec/transformers/bootblock.c
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <soc/intel/common/block/lpc/lpc_def.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <superio/aspeed/ast2400/ast2400.h>
+#include <superio/aspeed/common/aspeed.h>
+
+#define ASPEED_SIO_PORT 0x2E
+#define PCR_DMI_LPCIOD	0x2770
+#define PCR_DMI_LPCIOE	0x2774
+
+void bootblock_mainboard_early_init(void)
+{
+	/*
+	 * Set up decoding windows on PCH over PCR. The CPU uses two of AST2600 SIO ports,
+	 * one is connected to debug header (SUART1) and another is used as SOL (SUART2).
+	 * For ArcherCity CRB, only SUART1 is used.
+	 */
+	uint16_t lpciod = (LPC_IOD_COMB_RANGE | LPC_IOD_COMA_RANGE);
+	uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMB_EN | LPC_IOE_COMA_EN);
+
+	/* Open IO windows: 0x3f8 for com1 and 02f8 for com2 */
+	pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod);
+	/* LPC I/O enable: com1 and com2 */
+	pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe);
+
+	/* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */
+	pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod);
+	pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe);
+
+	const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1);
+	aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/inventec/transformers/devicetree.cb b/src/mainboard/inventec/transformers/devicetree.cb
new file mode 100644
index 0000000000..0c4d92e37a
--- /dev/null
+++ b/src/mainboard/inventec/transformers/devicetree.cb
@@ -0,0 +1,52 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip soc/intel/xeon_sp/spr
+	# configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs
+	register "turbo_ratio_limit" = "0x181819191e242424"
+	register "turbo_ratio_limit_cores" = "0x3836322e2a1c1a18"
+
+	device domain 0 on
+		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.1 on end # Management Engine Interface 2
+		device pci 16.6 on end # Management Engine IDE-R
+		device pci 1f.0 on         # Intel device 1b81: PCH eSPI controller
+			chip superio/common
+				device pnp 2e.0 on
+					chip superio/aspeed/ast2400
+						register "use_espi" = "1"
+						device pnp 2e.2 on      # SUART1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 2e.3 on      # SUART2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+						device pnp 2e.4 off      # System Wake-Up Control
+						end
+						device pnp 2e.5 off      # Keyboard controller
+						end
+						device pnp 2e.7 off      # GPIO
+						end
+						device pnp 2e.b off      # Com3
+						end
+						device pnp 2e.c off      # Com4
+						end
+						device pnp 2e.d off      # LPC 2 AHB
+						end
+						device pnp 2e.e off      # Mailbox
+						end
+					end
+				end
+			end
+			chip drivers/ipmi # BMC KCS
+				device pnp ca2.0 on end
+				register "bmc_i2c_address" = "0x20"
+				register "bmc_boot_timeout" = "60"
+				register "wait_for_bmc" = "1"
+			end
+			device pnp 0c31.0 off
+			end
+		end
+	end
+end
diff --git a/src/mainboard/inventec/transformers/dsdt.asl b/src/mainboard/inventec/transformers/dsdt.asl
new file mode 100644
index 0000000000..2204748ea2
--- /dev/null
+++ b/src/mainboard/inventec/transformers/dsdt.asl
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <acpi/dsdt_top.asl>
+	// platform ACPI tables
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	// SPR-SP ACPI tables
+	#include <soc/intel/xeon_sp/spr/acpi/uncore.asl>
+
+	// LPC related entries
+	Scope (\_SB.PC00)
+	{
+		#include <soc/intel/xeon_sp/spr/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/inventec/transformers/include/mainboard_ras.h b/src/mainboard/inventec/transformers/include/mainboard_ras.h
new file mode 100644
index 0000000000..76f38726e0
--- /dev/null
+++ b/src/mainboard/inventec/transformers/include/mainboard_ras.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_RAS_H
+#define MAINBOARD_RAS_H
+
+struct fru {
+	const char *str;
+};
+
+struct fru *mainboard_ras_get_ch_map(void);
+
+#endif
diff --git a/src/mainboard/inventec/transformers/include/sprsp_ac_iio.h b/src/mainboard/inventec/transformers/include/sprsp_ac_iio.h
new file mode 100644
index 0000000000..2dcf6c9a1c
--- /dev/null
+++ b/src/mainboard/inventec/transformers/include/sprsp_ac_iio.h
@@ -0,0 +1,142 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _SPRSP_AC_IIO_H_
+#define _SPRSP_AC_IIO_H_
+
+#include <defs_iio.h>
+
+/* For now only set 3 fields and hard-coded others, should be extended in the future */
+#define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp)	\
+	{						\
+		.SLOTEIP = 0,				\
+		.SLOTHPCAP = 0,				\
+		.SLOTHPSUP = 0,				\
+		.SLOTPIP = 0,				\
+		.SLOTAIP = 0,				\
+		.SLOTMRLSP = 0,				\
+		.SLOTPCP = 0,				\
+		.SLOTABP = 0,				\
+		.SLOTIMP = slotimp,			\
+		.SLOTSPLS = 0,				\
+		.SLOTSPLV = 0,				\
+		.SLOTPSP = slotpsp,			\
+		.VppEnabled = 0,			\
+		.VppPort = 0,				\
+		.VppAddress = 0,			\
+		.MuxAddress = 0,			\
+		.ChannelID = 0,				\
+		.PciePortEnable = 1,			\
+		.PEXPHIDE = pexphide,			\
+		.HidePEXPMenu = 0,			\
+		.PciePortOwnership = 0,			\
+		.RetimerConnectCount = 0,		\
+		.PcieMaxPayload = 0x7,			\
+		.PciePortLinkSpeed = 0,			\
+		.DfxDnTxPresetGen3 = 0xFF		\
+	}
+
+/*
+ * Standard ArcherCity IIO PCIe Port Table
+ */
+static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY ac_iio_pci_port_skt0[] = {
+	/* DMI port: array index 0 */
+	CFG_UPD_PCIE_PORT(0, 0, 0),
+	/* IOU0 (PE0): array index 1 ~ 8 */
+	CFG_UPD_PCIE_PORT(0, 1, 1), /* 15:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU1 (PE1): array index 9 ~ 16 */
+	CFG_UPD_PCIE_PORT(0, 1, 9), /* 26:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU2 (PE2): array index 17 ~ 24 */
+	CFG_UPD_PCIE_PORT(0, 1, 17), /* 37:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU3 (PE3): array index 25 ~ 32 */
+	CFG_UPD_PCIE_PORT(0, 1, 25), /* 48:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 27), /* 48:03.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 29), /* 48:05.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 31), /* 48:07.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU4 (PE4): array index 33 ~ 40 */
+	CFG_UPD_PCIE_PORT(0, 1, 33), /* 59:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 35), /* 59:03.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 37), /* 59:05.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 39), /* 59:07.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* ArcherCity doesn't use IOU5 ~ IOU6. */
+};
+
+static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY ac_iio_pci_port_skt1[] = {
+	/* DMI port: array index 0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU0 (PE0): array index 1 ~ 8 */
+	CFG_UPD_PCIE_PORT(0, 1, 1), /* 97:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU1 (PE1): array index 9 ~ 16 */
+	CFG_UPD_PCIE_PORT(0, 1, 9), /* a7:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU2 (PE2): array index 17 ~ 24 */
+	CFG_UPD_PCIE_PORT(0, 1, 17), /* b7:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU3 (PE3): array index 25 ~ 32 */
+	CFG_UPD_PCIE_PORT(0, 1, 25), /* c7:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 27), /* c7:03.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 29), /* c7:05.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 31), /* c7:07.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU4 (PE4): array index 33 ~ 40 */
+	CFG_UPD_PCIE_PORT(0, 1, 33), /* d7:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 35), /* d7:03.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 37), /* d7:05.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 39), /* d7:07.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* ArcherCity doesn't use IOU5 ~ IOU6. */
+};
+#endif /* _SPRSP_CL_IIO_H_ */
diff --git a/src/mainboard/inventec/transformers/include/sprsp_gpio.h b/src/mainboard/inventec/transformers/include/sprsp_gpio.h
new file mode 100644
index 0000000000..1a02b9fbed
--- /dev/null
+++ b/src/mainboard/inventec/transformers/include/sprsp_gpio.h
@@ -0,0 +1,261 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CFG_GPIO_H
+#define CFG_GPIO_H
+
+#include <gpio.h>
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPPC_A ------- */
+	_PAD_CFG_STRUCT(GPPC_A0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPPC_A1, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPPC_A2, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF), 0),
+	_PAD_CFG_STRUCT(GPPC_A3, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPPC_A4, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF), 0),
+	_PAD_CFG_STRUCT(GPPC_A5, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF), 0),
+	_PAD_CFG_STRUCT(GPPC_A6, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPPC_A7, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPPC_A8, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPPC_A9, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPPC_A10, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPPC_A11, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	PAD_CFG_GPO(GPPC_A12, 1, RSMRST),
+	PAD_NC(GPPC_A13, NONE),
+	PAD_NC(GPPC_A14, NONE),
+	PAD_CFG_GPO(GPPC_A15, 0, RSMRST),
+	_PAD_CFG_STRUCT(GPPC_A16, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF), 0),
+	PAD_NC(GPPC_A17, NONE),
+	PAD_CFG_GPO(GPPC_A18, 1, RSMRST),
+	/* GPPC_A19 - RESERVED */
+
+	/* ------- GPIO Group GPPC_B ------- */
+	_PAD_CFG_STRUCT(GPPC_B0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPPC_B1, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPPC_B2, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPPC_B3, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPPC_B4, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	PAD_NC(GPPC_B5, NONE),
+	_PAD_CFG_STRUCT(GPPC_B6, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B7, NONE, RSMRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B8, NONE, RSMRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPPC_B9, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B10, NONE, RSMRST, OFF, ACPI),
+	/* GPPC_B11 - n/a */
+	PAD_NC(GPPC_B12, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B13, NONE, RSMRST, OFF, ACPI),
+	PAD_NC(GPPC_B14, NONE),
+	PAD_NC(GPPC_B15, NONE),
+	PAD_NC(GPPC_B16, NONE),
+	PAD_NC(GPPC_B17, NONE),
+	PAD_NC(GPPC_B18, NONE),
+	PAD_NC(GPPC_B19, NONE),
+	PAD_NC(GPPC_B20, NONE),
+	PAD_NC(GPPC_B21, NONE),
+	PAD_NC(GPPC_B22, NONE),
+	_PAD_CFG_STRUCT(GPPC_B23, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+
+	/* ------- GPIO Group GPPC_S ------- */
+	PAD_NC(GPPC_S0, NONE),
+	_PAD_CFG_STRUCT(GPPC_S1, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_NC(GPPC_S2, NONE),
+	PAD_CFG_GPO(GPPC_S3, 1, RSMRST),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_S4, NONE, RSMRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPPC_S5, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_NC(GPPC_S6, NONE),
+	_PAD_CFG_STRUCT(GPPC_S7, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPPC_S8, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPPC_S9, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPPC_S10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_S11, NONE, RSMRST, OFF, ACPI),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPPC_C ------- */
+	/* GPPC_C0 - RESERVED */
+	/* GPPC_C1 - RESERVED */
+	_PAD_CFG_STRUCT(GPPC_C2, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),
+	/* GPPC_C3 - RESERVED */
+	/* GPPC_C4 - RESERVED */
+	PAD_CFG_GPO(GPPC_C5, 0, DEEP),
+	/* GPPC_C6 - RESERVED */
+	/* GPPC_C7 - RESERVED */
+	/* GPPC_C8 - RESERVED */
+	/* GPPC_C9 - RESERVED */
+	/* GPPC_C10 - RESERVED */
+	/* GPPC_C11 - RESERVED */
+	/* GPPC_C12 - RESERVED */
+	/* GPPC_C13 - RESERVED */
+	/* GPPC_C14 - RESERVED */
+	/* GPPC_C15 - RESERVED */
+	/* GPPC_C16 - RESERVED */
+	PAD_CFG_GPO(GPPC_C17, 1, DEEP),
+	PAD_CFG_GPO(GPPC_C18, 0, RSMRST),
+	_PAD_CFG_STRUCT(GPPC_C19, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPPC_C20, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | (1 << 1), 0),
+	PAD_CFG_GPO(GPPC_C21, 0, DEEP),
+
+	/* ------- GPIO Group GPP_D ------- */
+	_PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | (1 << 1), 0),
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
+	PAD_NC(GPP_D3, UP_20K),
+	PAD_NC(GPP_D4, UP_20K),
+	PAD_NC(GPP_D5, UP_20K),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, RSMRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, RSMRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	PAD_NC(GPP_D9, UP_20K),
+	PAD_NC(GPP_D10, NONE),
+	_PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	/* GPP_D13 - RESERVED */
+	_PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_NC(GPP_D15, NONE),
+	_PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, RSMRST, OFF, ACPI),
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPO(GPP_E0, 0, RSMRST),
+	PAD_CFG_GPO(GPP_E1, 1, RSMRST),
+	PAD_CFG_GPO(GPP_E2, 1, RSMRST),
+	PAD_CFG_GPO(GPP_E3, 1, RSMRST),
+	_PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_E13, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	PAD_CFG_GPO(GPP_E14, 0, RSMRST),
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	_PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_E18, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	/* ------- GPIO Group JTAG ------- */
+
+	/* ------- GPIO Community 4 ------- */
+
+	/* ------- GPIO Group GPPC_H ------- */
+	_PAD_CFG_STRUCT(GPPC_H0, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	/* GPPC_H1 - RESERVED */
+	PAD_NC(GPPC_H2, UP_20K),
+	PAD_NC(GPPC_H3, UP_20K),
+	PAD_NC(GPPC_H4, UP_20K),
+	PAD_NC(GPPC_H5, UP_20K),
+	_PAD_CFG_STRUCT(GPPC_H6, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPPC_H7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_NC(GPPC_H8, UP_20K),
+	PAD_NC(GPPC_H9, NONE),
+	PAD_NC(GPPC_H10, NONE),
+	PAD_NC(GPPC_H11, NONE),
+	PAD_NC(GPPC_H12, UP_20K),
+	PAD_NC(GPPC_H13, UP_20K),
+	PAD_NC(GPPC_H14, UP_20K),
+	_PAD_CFG_STRUCT(GPPC_H15, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPPC_H16, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPPC_H17, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_NC(GPPC_H18, NONE),
+	_PAD_CFG_STRUCT(GPPC_H19, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+	/* ------- GPIO Group GPP_J ------- */
+	_PAD_CFG_STRUCT(GPP_J0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_1K)),
+	_PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_J4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_J5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_J6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_1K)),
+	_PAD_CFG_STRUCT(GPP_J7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_1K)),
+	_PAD_CFG_STRUCT(GPP_J8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	PAD_NC(GPP_J9, DN_20K),
+	PAD_NC(GPP_J10, DN_20K),
+	PAD_NC(GPP_J11, DN_20K),
+	PAD_NC(GPP_J12, UP_1K),
+	PAD_NC(GPP_J13, UP_1K),
+	PAD_NC(GPP_J14, UP_1K),
+	PAD_NC(GPP_J15, UP_1K),
+
+	/* ------- GPIO Community 5 ------- */
+
+	/* ------- GPIO Group GPP_I ------- */
+	PAD_NC(GPP_I0, UP_20K),
+	PAD_NC(GPP_I1, UP_20K),
+	PAD_NC(GPP_I2, UP_20K),
+	PAD_NC(GPP_I3, UP_20K),
+	PAD_NC(GPP_I4, UP_20K),
+	PAD_NC(GPP_I5, UP_20K),
+	PAD_NC(GPP_I6, UP_20K),
+	PAD_NC(GPP_I7, UP_20K),
+	PAD_NC(GPP_I8, UP_20K),
+	PAD_CFG_TERM_GPO(GPP_I9, 0, UP_20K, DEEP),
+	PAD_NC(GPP_I10, UP_20K),
+	PAD_CFG_TERM_GPO(GPP_I11, 0, UP_20K, DEEP),
+	_PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_I15, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_I16, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_I17, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	PAD_CFG_TERM_GPO(GPP_I18, 0, UP_20K, DEEP),
+	PAD_CFG_TERM_GPO(GPP_I19, 0, UP_20K, DEEP),
+	PAD_CFG_TERM_GPO(GPP_I20, 0, UP_20K, DEEP),
+	PAD_CFG_TERM_GPO(GPP_I21, 0, UP_20K, DEEP),
+	_PAD_CFG_STRUCT(GPP_I22, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I23, NONE, RSMRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_L ------- */
+	_PAD_CFG_STRUCT(GPP_L0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	/* GPP_L1 - RESERVED */
+	_PAD_CFG_STRUCT(GPP_L2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
+	PAD_NC(GPP_L3, NONE),
+	PAD_NC(GPP_L4, NONE),
+	_PAD_CFG_STRUCT(GPP_L5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_L6, NONE, PLTRST, OFF, DRIVER),
+	PAD_NC(GPP_L7, NONE),
+	PAD_NC(GPP_L8, NONE),
+
+	/* ------- GPIO Group GPP_M ------- */
+	PAD_CFG_GPI_TRIG_OWN(GPP_M0, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M1, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M2, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M3, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M4, DN_20K, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M5, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M6, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M7, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M8, NONE, PLTRST, OFF, ACPI),
+	PAD_NC(GPP_M9, DN_20K),
+	PAD_NC(GPP_M10, DN_20K),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M11, NONE, RSMRST, OFF, ACPI),
+	PAD_CFG_TERM_GPO(GPP_M12, 0, DN_20K, DEEP),
+	PAD_NC(GPP_M13, DN_20K),
+	PAD_NC(GPP_M14, DN_20K),
+	PAD_NC(GPP_M15, UP_20K),
+	PAD_NC(GPP_M16, UP_20K),
+	PAD_NC(GPP_M17, UP_20K),
+
+	/* ------- GPIO Group GPP_N ------- */
+	PAD_NC(GPP_N0, NONE),
+	PAD_NC(GPP_N1, DN_20K),
+	PAD_NC(GPP_N2, NONE),
+	PAD_NC(GPP_N3, NONE),
+	PAD_NC(GPP_N4, NONE),
+};
+
+#endif /* CFG_GPIO_H */
diff --git a/src/mainboard/inventec/transformers/ipmi.c b/src/mainboard/inventec/transformers/ipmi.c
new file mode 100644
index 0000000000..fd46ff443d
--- /dev/null
+++ b/src/mainboard/inventec/transformers/ipmi.c
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <drivers/ipmi/ipmi_if.h>
+#include <drivers/ipmi/ipmi_ops.h>
+#include <drivers/ipmi/ocp/ipmi_ocp.h>
+#include <drivers/ocp/include/vpd.h>
+#include <drivers/vpd/vpd.h>
+#include <types.h>
+
+#include "ipmi.h"
+
+enum cb_err ipmi_get_slot_id(uint8_t *slot_id)
+{
+	int ret;
+	struct ipmi_config_rsp {
+		struct ipmi_rsp resp;
+		uint8_t board_sku_id;
+		uint8_t board_rev_id;
+		uint8_t slot_id;
+		uint8_t slot_config_id;
+	} __packed;
+	struct ipmi_config_rsp rsp;
+
+	ret = ipmi_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_GET_BOARD_ID, NULL, 0, (unsigned char *)&rsp, sizeof(rsp));
+
+	if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) {
+		printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", __func__, ret, rsp.resp.completion_code);
+		return CB_ERR;
+	}
+	*slot_id = rsp.slot_id;
+	return CB_SUCCESS;
+}
+
+void init_frb2_wdt(void)
+{
+	uint8_t enable;
+	int action, countdown;
+
+	if (vpd_get_bool(FRB2_TIMER, VPD_RW_THEN_RO, &enable)) {
+		printk(BIOS_DEBUG, "Got VPD %s value: %d\n", FRB2_TIMER, enable);
+	} else {
+		printk(BIOS_INFO, "Not able to get VPD %s, default set to %d\n", FRB2_TIMER,
+			FRB2_TIMER_DEFAULT);
+		enable = FRB2_TIMER_DEFAULT;
+	}
+
+	if (enable) {
+		if (vpd_get_int(FRB2_COUNTDOWN, VPD_RW_THEN_RO, &countdown)) {
+			printk(BIOS_DEBUG, "FRB2 timer countdown set to: %d ms\n",
+				countdown * 100);
+		} else {
+			printk(BIOS_DEBUG, "FRB2 timer use default value: %d ms\n",
+				FRB2_COUNTDOWN_DEFAULT * 100);
+			countdown = FRB2_COUNTDOWN_DEFAULT;
+		}
+
+		if (vpd_get_int(FRB2_ACTION, VPD_RW_THEN_RO, &action)) {
+			printk(BIOS_DEBUG, "FRB2 timer action set to: %d\n", action);
+		} else {
+			printk(BIOS_DEBUG, "FRB2 timer action use default value: %d\n",
+				FRB2_ACTION_DEFAULT);
+			action = FRB2_ACTION_DEFAULT;
+		}
+		ipmi_init_and_start_bmc_wdt(CONFIG_BMC_KCS_BASE, (uint16_t)countdown,
+			(uint8_t)action);
+	} else {
+		printk(BIOS_DEBUG, "Disable FRB2 timer\n");
+		ipmi_stop_bmc_wdt(CONFIG_BMC_KCS_BASE);
+	}
+}
diff --git a/src/mainboard/inventec/transformers/ipmi.h b/src/mainboard/inventec/transformers/ipmi.h
new file mode 100644
index 0000000000..076ca20c54
--- /dev/null
+++ b/src/mainboard/inventec/transformers/ipmi.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef TRANSFORMERS_IPMI_H
+#define TRANSFORMERS_IPMI_H
+
+#include <types.h>
+
+void init_frb2_wdt(void);
+enum cb_err ipmi_get_slot_id(uint8_t *slot_id);
+
+#endif
diff --git a/src/mainboard/inventec/transformers/ramstage.c b/src/mainboard/inventec/transformers/ramstage.c
new file mode 100644
index 0000000000..44539645a8
--- /dev/null
+++ b/src/mainboard/inventec/transformers/ramstage.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include <sprsp_gpio.h>
+#include <intelblocks/cse.h>
+#include <memory_info.h>
+
+#include "ipmi.h"
+
+#define SLOT_ID_LEN 2
+static char slot_id_str[SLOT_ID_LEN];
+extern uint32_t heci_fw_sts(void);
+extern uint32_t  heci_cse_normal(void);
+extern uint32_t heci_cse_done(void);
+
+//extern void cse_init(uintptr_t tempbar);
+
+u8 smbios_mainboard_feature_flags(void)
+{
+	return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE;
+}
+
+const char *smbios_mainboard_location_in_chassis(void)
+{
+	uint8_t slot_id = 0;
+	if (ipmi_get_slot_id(&slot_id) != CB_SUCCESS) {
+		printk(BIOS_ERR, "IPMI get slot_id failed\n");
+		return "Part Component";
+	}
+	return slot_id_str;
+}
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+    /* configure Emmitsburg PCH GPIO controller after FSP-M */
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/inventec/transformers/romstage.c b/src/mainboard/inventec/transformers/romstage.c
new file mode 100644
index 0000000000..c04720a5e3
--- /dev/null
+++ b/src/mainboard/inventec/transformers/romstage.c
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <drivers/vpd/vpd.h>
+#include <drivers/ocp/include/vpd.h>
+#include <drivers/ipmi/ipmi_if.h>
+#include <drivers/ipmi/ocp/ipmi_ocp.h>
+#include <drivers/ocp/ewl/ocp_ewl.h>
+#include <soc/romstage.h>
+#include <defs_cxl.h>
+#include <defs_iio.h>
+#include <sprsp_ac_iio.h>
+
+#include "ipmi.h"
+
+void mainboard_ewl_check(void)
+{
+	/* Enhanced Warning Log prints EWL type 3 primarily associated with MRC training failures */
+	get_ewl();
+}
+
+static void mainboard_config_iio(FSPM_UPD *mupd)
+{
+	int port;
+
+	UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig =
+		(UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr;
+
+	/* Socket0: Array ac_iio_pci_port_skt0 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */
+	for (port = 0; port < ARRAY_SIZE(ac_iio_pci_port_skt0); port++) {
+		PciePortConfig[0].SLOTIMP[port] = ac_iio_pci_port_skt0[port].SLOTIMP;
+		PciePortConfig[0].SLOTPSP[port] = ac_iio_pci_port_skt0[port].SLOTPSP;
+		PciePortConfig[0].PciePortEnable[port] = ac_iio_pci_port_skt0[port].PciePortEnable;
+		PciePortConfig[0].PEXPHIDE[port] = ac_iio_pci_port_skt0[port].PEXPHIDE;
+		PciePortConfig[0].PcieMaxPayload[port] = ac_iio_pci_port_skt0[port].PcieMaxPayload;
+		PciePortConfig[0].PciePortLinkSpeed[port] = ac_iio_pci_port_skt0[port].PciePortLinkSpeed;
+		PciePortConfig[0].DfxDnTxPresetGen3[port] = ac_iio_pci_port_skt0[port].DfxDnTxPresetGen3;
+	}
+	/* Socket0: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */
+	for (port = ARRAY_SIZE(ac_iio_pci_port_skt0); port < MAX_IIO_PORTS_PER_SOCKET; port++) {
+		PciePortConfig[0].PEXPHIDE[port] = 1;
+		PciePortConfig[0].HidePEXPMenu[port] = 1;
+	}
+	PciePortConfig[0].ConfigIOU[0] = IIO_BIFURCATE_xxxxxx16;
+	PciePortConfig[0].ConfigIOU[1] = IIO_BIFURCATE_xxxxxx16;
+	PciePortConfig[0].ConfigIOU[2] = IIO_BIFURCATE_xxxxxx16;
+	PciePortConfig[0].ConfigIOU[3] = IIO_BIFURCATE_xxx8xxx8;
+	PciePortConfig[0].ConfigIOU[4] = IIO_BIFURCATE_xxxxxx16;
+
+	PciePortConfig[0].PcieGlobalAspm = 0x1;
+	PciePortConfig[0].PcieMaxReadRequestSize = 0x5;
+
+	/* Socket1: Array ac_iio_pci_port_skt1 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */
+	for (port = 0; port < ARRAY_SIZE(ac_iio_pci_port_skt1); port++) {
+		PciePortConfig[1].SLOTIMP[port] = ac_iio_pci_port_skt1[port].SLOTIMP;
+		PciePortConfig[1].SLOTPSP[port] = ac_iio_pci_port_skt1[port].SLOTPSP;
+		PciePortConfig[1].PciePortEnable[port] = ac_iio_pci_port_skt1[port].PciePortEnable;
+		PciePortConfig[1].PEXPHIDE[port] = ac_iio_pci_port_skt1[port].PEXPHIDE;
+		PciePortConfig[1].PcieMaxPayload[port] = ac_iio_pci_port_skt1[port].PcieMaxPayload;
+		PciePortConfig[1].PciePortLinkSpeed[port] = ac_iio_pci_port_skt1[port].PciePortLinkSpeed;
+		PciePortConfig[1].DfxDnTxPresetGen3[port] = ac_iio_pci_port_skt1[port].DfxDnTxPresetGen3;
+	}
+	/* Socket1: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */
+	for (port = ARRAY_SIZE(ac_iio_pci_port_skt1); port < MAX_IIO_PORTS_PER_SOCKET; port++) {
+		PciePortConfig[1].PEXPHIDE[port] = 1;
+		PciePortConfig[1].HidePEXPMenu[port] = 1;
+	}
+	PciePortConfig[1].ConfigIOU[0] = IIO_BIFURCATE_x4x4x4x4;
+	PciePortConfig[1].ConfigIOU[1] = IIO_BIFURCATE_xxxxxx16;
+	PciePortConfig[1].ConfigIOU[2] = IIO_BIFURCATE_xxxxxx16;
+	PciePortConfig[1].ConfigIOU[3] = IIO_BIFURCATE_xxxxxx16;
+	PciePortConfig[1].ConfigIOU[4] = IIO_BIFURCATE_xxx8xxx8;
+
+	PciePortConfig[1].PcieGlobalAspm = 0x1;
+	PciePortConfig[1].PcieMaxReadRequestSize = 0x5;
+
+	/* If CONFIG(OCP_VPD) is not enabled or CXL is explicitly disabled, don't enable CXL */
+	if (!CONFIG(OCP_VPD) || get_cxl_mode_from_vpd() == CXL_DISABLED) {
+		printk(BIOS_DEBUG, "Don't enable CXL via VPD %s\n", CXL_MODE);
+	} else {
+		/* Set socket 0 IIO PCIe PE1 to CXL mode */
+		/* Set socket 1 IIO PCIe PE0 to CXL mode */
+		/* eg. Protocl Auto Negotiation */
+		mupd->FspmConfig.IioPcieSubSystemMode1[0] = IIO_MODE_CXL;
+		mupd->FspmConfig.IioPcieSubSystemMode0[1] = IIO_MODE_CXL;
+
+		/* Disable CXL header bypass */
+		mupd->FspmConfig.DfxCxlHeaderBypass = 0;
+
+		/* Set DFX CXL security level to fully trusted */
+		mupd->FspmConfig.DfxCxlSecLvl = CXL_SECURITY_FULLY_TRUSTED;
+
+		/* Set DelayAfterPCIeLinkTraining to 2000 ms */
+		mupd->FspmConfig.DelayAfterPCIeLinkTraining = 2000;
+	}
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	uint8_t val;
+
+	/* Since it's the first IPMI command, it's better to run get BMC selftest result first */
+	if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) {
+		init_frb2_wdt();
+	}
+
+	/* Send FSP log message to SOL */
+	if (CONFIG(VPD) && vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val))
+		mupd->FspmConfig.SerialIoUartDebugEnable = val;
+	else {
+		printk(BIOS_INFO, "Not able to get VPD %s, default set "
+			"SerialIoUartDebugEnable to %d\n", FSP_LOG, FSP_LOG_DEFAULT);
+		mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT;
+	}
+
+	/* Set Rank Margin Tool to disable. */
+	mupd->FspmConfig.EnableRMT = 0x0;
+	/* Enable - Portions of memory reference code will be skipped when possible to increase boot speed on warm boots */
+	/* Disable - Disables this feature */
+	/*Auto - Sets it to the MRC default setting */
+	mupd->FspmConfig.AttemptFastBoot = 0x1;
+	/* Set Attempt Fast Cold Boot to enable */
+	/* Enable - Portions of memory reference code will be skipped when possible to increase boot speed on cold boots */
+	/* Disable - Disables this feature */
+	/* Auto - Sets it to the MRC default setting */
+	mupd->FspmConfig.AttemptFastBootCold = 0x1;
+
+	/* Set Adv MemTest Option to 0. */
+	mupd->FspmConfig.AdvMemTestOptions = 0x0;
+	/* Set MRC Promote Warnings to disable. */
+	/* Determines if MRC warnings are promoted to system level. */
+	mupd->FspmConfig.promoteMrcWarnings = 0x0;
+	/* Set Promote Warnings to disable. */
+	/* Determines if warnings are promoted to system level. */
+	mupd->FspmConfig.promoteWarnings = 0x0;
+
+	/* Reduce FSP debug message to Minimum */
+	mupd->FspmConfig.serialDebugMsgLvl = 0x1;
+
+	/* Disable FSP memory train results */
+	mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0;
+
+	mainboard_config_iio(mupd);
+}