diff options
| author | Sukumar Ghorai <sukumar.ghorai@intel.com> | 2023-07-06 15:23:32 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-12 14:10:54 +0000 |
| commit | 211e391a8295d48495ba5e4ebcde11ec85ed317f (patch) | |
| tree | 46596b47bc6abb601b17bfdfd821ca284512f968 /src/mainboard | |
| parent | b2b18e10643328da2df1d21e4a63de5d237adb26 (diff) | |
mb/{google, intel}: Enable PCH Energy Reporting for MTL platforms
This patch enables PCH to CPU energy report feature which can be used
by Intel Telemetry Driver.
BUG=b:269563588
TEST=Able to build and boot google/rex and perform below check to ensure
the energy reporting is correct
w/o this cl:
# lspci -s 00:14.2 -vvv | grep "Region 0"
Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K]
# iotools mmio_read32 0x957f8068 #i.e., 104th offset
0xXXXX0000
w/ this cl:
#lspci -s 00:14.2 -vvv | grep "Region 0"
Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K]
# iotools mmio_read32 0x957f8068 #i.e., 104th offset
0xXXXXfc004
Change-Id: I9bd4625ea311a05071878aaec68433a1ba018c0d
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76353
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Diffstat (limited to 'src/mainboard')
3 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index 4297c8714a..25befb4dd4 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -33,6 +33,9 @@ chip soc/intel/meteorlake # S0ix enable register "s0ix_enable" = "1" + # Enable Energy Reporting + register "pch_pm_energy_report_enable" = "1" + # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 1b37784bcd..57a5288261 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -33,6 +33,9 @@ chip soc/intel/meteorlake # S0ix enable register "s0ix_enable" = "1" + # Enable Energy Reporting + register "pch_pm_energy_report_enable" = "1" + # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index b7ce90daeb..f8f61a5611 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -52,6 +52,9 @@ chip soc/intel/meteorlake # Enable S0ix register "s0ix_enable" = "1" + # Enable energy reporting + register "pch_pm_energy_report_enable" = "1" + # Enable EDP in PortA register "ddi_port_A_config" = "1" # Enable HDMI in Port B @@ -334,6 +337,7 @@ chip soc/intel/meteorlake .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, }" end # PCIE11 SSD Gen4 + device ref ioe_shared_sram on end device ref xhci on chip drivers/usb/acpi device ref xhci_root_hub on |