diff options
| author | Tim Crawford <tcrawford@system76.com> | 2023-07-13 09:44:09 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-18 15:00:09 +0000 |
| commit | ff865a329f9f04ed3740b2f7f128fab91886c01c (patch) | |
| tree | 3bcc7b413334659c8db1fdb76bb89416568c8610 /src/mainboard | |
| parent | f501128536ca158d4a12a9afe6ea24e6ceb6506c (diff) | |
mb/system76/adl: Switch from S0ix to S3
After fixing TPM logs clobbering other regions in CB:73297, S3 no longer
causes cache issues resulting in power off after multiple suspends.
This is required for disabling Intel CSME by default.
Change-Id: I7eef4c883fd65db93dae81adabd895b2de90496a
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/system76/adl/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/system76/adl/devicetree.cb | 2 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/system76/adl/Kconfig b/src/mainboard/system76/adl/Kconfig index 49a7b2b226..5a28701187 100644 --- a/src/mainboard/system76/adl/Kconfig +++ b/src/mainboard/system76/adl/Kconfig @@ -7,6 +7,7 @@ config BOARD_SYSTEM76_ADL_COMMON select DRIVERS_INTEL_PMC select DRIVERS_INTEL_USB4_RETIMER select EC_SYSTEM76_EC + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE @@ -101,6 +102,9 @@ config MAINBOARD_VERSION config CONSOLE_POST default y +config D3COLD_SUPPORT + default n + config DIMM_SPD_SIZE default 512 diff --git a/src/mainboard/system76/adl/devicetree.cb b/src/mainboard/system76/adl/devicetree.cb index d469491884..c33483959a 100644 --- a/src/mainboard/system76/adl/devicetree.cb +++ b/src/mainboard/system76/adl/devicetree.cb @@ -11,8 +11,6 @@ chip soc/intel/alderlake # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" - register "s0ix_enable" = "1" - # Enable C6 DRAM register "enable_c6dram" = "1" |