From ff865a329f9f04ed3740b2f7f128fab91886c01c Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Thu, 13 Jul 2023 09:44:09 -0600 Subject: mb/system76/adl: Switch from S0ix to S3 After fixing TPM logs clobbering other regions in CB:73297, S3 no longer causes cache issues resulting in power off after multiple suspends. This is required for disabling Intel CSME by default. Change-Id: I7eef4c883fd65db93dae81adabd895b2de90496a Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/73353 Tested-by: build bot (Jenkins) Reviewed-by: Jeremy Soller --- src/mainboard/system76/adl/Kconfig | 4 ++++ src/mainboard/system76/adl/devicetree.cb | 2 -- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/system76/adl/Kconfig b/src/mainboard/system76/adl/Kconfig index 49a7b2b226..5a28701187 100644 --- a/src/mainboard/system76/adl/Kconfig +++ b/src/mainboard/system76/adl/Kconfig @@ -7,6 +7,7 @@ config BOARD_SYSTEM76_ADL_COMMON select DRIVERS_INTEL_PMC select DRIVERS_INTEL_USB4_RETIMER select EC_SYSTEM76_EC + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE @@ -101,6 +102,9 @@ config MAINBOARD_VERSION config CONSOLE_POST default y +config D3COLD_SUPPORT + default n + config DIMM_SPD_SIZE default 512 diff --git a/src/mainboard/system76/adl/devicetree.cb b/src/mainboard/system76/adl/devicetree.cb index d469491884..c33483959a 100644 --- a/src/mainboard/system76/adl/devicetree.cb +++ b/src/mainboard/system76/adl/devicetree.cb @@ -11,8 +11,6 @@ chip soc/intel/alderlake # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" - register "s0ix_enable" = "1" - # Enable C6 DRAM register "enable_c6dram" = "1" -- cgit v1.2.3