diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-11-18 17:33:45 +0100 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-07-17 03:22:46 +0000 |
| commit | cd3a99eaf96ac632426aff0b838f62b72ee3ca12 (patch) | |
| tree | 3dae2c7cbccbe229428ab615ab645ab374791b81 /src/mainboard | |
| parent | 1f17ba55632d0811c0c061408cb29144bed5ecac (diff) | |
mb/msi/ms7d25: Disable DMI ASPM
Disable DMI link ASPM which can degrade performance of overall system.
Desktop does not need to be concerned that much about idle power
consumption.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I60af9d2ab2913db449059e1e007999fa2f307f5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69826
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/msi/ms7d25/mainboard.c | 3 | ||||
| -rw-r--r-- | src/mainboard/msi/ms7d25/romstage_fsp_params.c | 2 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/msi/ms7d25/mainboard.c b/src/mainboard/msi/ms7d25/mainboard.c index ee781d5856..7e865331ef 100644 --- a/src/mainboard/msi/ms7d25/mainboard.c +++ b/src/mainboard/msi/ms7d25/mainboard.c @@ -78,6 +78,9 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) params->PcieRpFunctionSwap = 0; params->CpuPcieRpFunctionSwap = 0; + params->PchLegacyIoLowLatency = 1; + params->PchDmiAspmCtrl = 0; + params->CpuPcieRpPmSci[0] = 1; // M2_1 params->CpuPcieRpPmSci[1] = 1; // PCI_E1 params->PcieRpPmSci[0] = 1; // PCI_E2 diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c index b9b8206b83..833ff1ac97 100644 --- a/src/mainboard/msi/ms7d25/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c @@ -55,6 +55,8 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = 1; memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = 0; memupd->FspmConfig.DmiMaxLinkSpeed = 4; // Gen4 speed, undocumented + memupd->FspmConfig.DmiAspm = 0; + memupd->FspmConfig.DmiAspmCtrl = 0; memupd->FspmConfig.SkipExtGfxScan = 0; memupd->FspmConfig.PchHdaSdiEnable[0] = 1; |