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This patch removes the static kconfig being used to fill in TME enable
FSP UPD. Instead use`is_tme_supported()` and `CONFIG(INTEL_TME)` to check
if the CPU has required TME support rather than hardcoding.
TEST=FSP debug log shows `TmeEnable` UPD is set appropriately for the
TME-supported CPU SKUs.
As per FSP-M debug log:
Without this CL, Alder Lake-P CPU SKU without TME support:
[SPEW ] TmeEnable = 0x1
With this CL, Alder Lake-P CPU SKU without TME support:
[SPEW ] TmeEnable = 0x0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8aa2922baaf2a49e6e2762d31eaffa7bdcd43b0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66750
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reading firmware_version register is supported on Ti50 version
0.22.4. Therefore correct the help text of the Kconfig option
TI50_FIRMWARE_VERSION_NOT_SUPPORTED.
Also change the message level to BIOS_WARNING.
BUG=b:234533588
TEST=emerge-corsola coreboot
BRANCH=none
Change-Id: I66a0ef896c9dc4cd0f586555a55dbcd1cfd863f9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66906
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Pronin <apronin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Reading Ti50 version is now supported on Ti50 version 0.22.4. Therefore
stop selecting TI50_FIRMWARE_VERSION_NOT_SUPPORTED for corsola.
BUG=b:234533588
TEST=emerge-corsola coreboot
TEST=cbmem -1 | grep 'Firmware version'
BRANCH=none
Change-Id: Id8d849eaf99542363c64e27411549eb6dddfd059
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66905
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Pronin <apronin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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1. Moved CHROMEEC_* to common (required for all boards)
2. added missing EC_GOOGLE_CHROMEEC_SKUID
TEST=Verified with simics on RVP
Change-Id: I26a01e5d1c78d4cd83b1aa53e68b2c3059da6061
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66762
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As per the Alder Lake FAS coreboot shall detect the existence of TME
feature by running the CPUID instruction:
CPUID leaf 7/sub-leaf 0
Return Value in ECX [bit 13]=1
If TME is supported then only access to TME MSRs are allowed otherwise
accessing those MSRs would result in GP#.
TEST=Able to detect the existence of TME feature across different
Alder Lake and Meteor Lake CPU SKUs.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibd4fcf15a66d27748ac7fbb52b18d7264b901cd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66749
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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The `INTEL_TME` Kconfig option has a prompt, which means it is meant to
be user-configurable. However, it has been selected from Alder Lake and
Meteor Lake Kconfig, so `INTEL_TME` cannot be disabled on them. Replace
the `select INTEL_TME` statements with default values in order for this
option to be user-configurable on all platforms that support it.
Change-Id: Ib37c108fcc1004840b82be18fd23c340a68ca748
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66756
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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This reverts commit 2b19d547c0866fef84bdb7b226ce7a4ac81af64f.
A power and performance analysis performed on Alder Lake demonstrated
that with an EPP (Energy Performance Preference) at 50% along with
EET (Energy Efficient Turbo) disabled, the overall SoC performance are
similar or better and the SoC uses less power.
For instance some browser benchmark results improved by 2% and some
multi-core tests by 4% while at the same time power consumption
lowered by approximately 7.6%.
BUG=b:240669428
TEST=verify that EPP is back to the by default 50% setting
`iotools rdmsr 0 0x774'
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I76d3914e51c5320af4c202558e1e7c57b7c0de54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
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Enable DPTF oem_variables and override based on CPU match id.
BUG=b:236294162
TEST=emerge-brask coreboot and check the value in odvp0 is correct.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ic935ec42f4de0cbec996da37b44f354978fe4b62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66907
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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bypass power
Add FW_CONFIG probe to separate ext fivr settings for Pujjoteen
and others(Pujjo and Pujjoflex)
BUG=b:242663554
TEST=Boot to OS and verify that ext_fivr_settings are set based on
fw_config.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I6bb6d1701c55459cf331dd2f3ffe07f91bca2fa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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The current reset delay is not enough to make touchscreen IC ready,
ILITEK feedback their requiremt is 400ms in spec T2.
After changing the reset_delay_ms and check touchscreen works,
ILITE also change the IRO to low level trigger.
This CL is to reflect that.
BUG=b:235929123
BRANCH=firmware-dedede-13606.B
TEST=check touchscreen function work
Change-Id: I126b2d74c1d7a1799e2f67a8ab01cba074447c06
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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Configure GPIOs according to schematics.
BUG=b:242277219
TEST=emerge-nissa coreboot
Change-Id: Id7412059ba98d58f7014ab7201ea8958ede5905e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Update Devicetree according to yaviks's design.
BUG=b:242277219
TEST=emerge-nissa coreboot
Change-Id: I5d91cccbb44787bcbe7258a817ff97b6dce86c2e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Output should be easier to read as a table.
Change-Id: I32e3e0aab5afd25c0b004d18f64de76445d9a0ed
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Disable INTEL_LPSS_UART_FOR_CONSOLE to stop debug output on UART 2.
This decreases boot time on all boards by around 60%.
TGL before:
Total Time: 10,110,807
TGL after:
Total Time: 3,851,641
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8f8d5cd46e87e7dafe0669b4a29c872b1789eb60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The ALC269 does not support the hardware equaliser, so remove the
entries related to this, as they have no effect.
Revert to the ALC269 defaults which work correctly with Linux. This
also corrects the subsystem id from 0x10ec111e to 0x10ec10d0.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I82647f67730ec344591f7dbd759a421c116d4fdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add ELAN touch support
BUG=b:243120074
TEST=emerge coreboot and check ELAN touch screen is workable
Change-Id: If30232b3da9af0015d6d87535b53f905c5a30bcb
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66912
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Isaac Lee <isaaclee@google.com>
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smn_read32 is used in this file, so include the header file with the
function prototype so that the file compiles successfully.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5bef96cd08f22b3475e8b5ba4e984a6e1ab4da36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Since the I2C controller is part of the FCH, move the early
initialization from bootblock.c to early_fch.c which also matches what
the newer AMD SoCs do.
TEST=Successfully boots on google/liara and all I2C/cr50/TPM functions
appear to work properly
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22d3a8888eaa34ea612da719c408c0083769e806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66866
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The functionality of sb_enable_lpc is implemented in the common LPC
support code as lpc_enable_controller. This gets called by the common
lpc_early_init which also calls lpc_disable_decodes and lpc_set_spibase.
The lpc_set_spibase call was already done in bootblock_fch_early_init,
so the main change in code behavior is that now lpc_disable_decodes gets
called during early FCH initialization. The lpc_enable_port80 and
sb_lpc_decode calls after the lpc_early_init code will reenable some of
the decodes.
TEST=Successfully boots on google/liara, cbmem and dmesg logs look clean
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia58a6f609fa149a6c09ed99f08bdc4f05eb56f96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66841
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I35dd9a2f0520077913bd3d8f408206dea1b30acb
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66867
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The PCI config space of the SMBus device has a secondary mapping as an
ACPIMMIO bank. Since the PCI device is on bus 0, it's already available
early in boot after the enable_pci_mmconf call, so there's no need to
use the ACPIMMIO mapping instead of the PCI config space mapping.
Verstage on PSP could theoretically access the PCI config space via the
0xcf8/0xcfc register pair, but since verstage on PSP doesn't have the
ACPIMMIO mapping anyway, we won't loose any functionality here.
Change-Id: I5c8ce8de0a6ab0ed41e7e8a5980d0f0510aaa993
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib203451bb3da06efd1d3f6e48496b370d81f4b7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66196
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GLKs chipset configures the devices, so use these aliases and remove
the entries when they are identical.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic29e5305346c3b7fbf66b027754a9ddd16b16269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66195
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DPTF Policy and temperature sensor values from thermal team.
BUG=b:242797681
TEST=build FW and boot to OS.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Id4365f87843a4408ae457e7ef27291fdaa0d5bde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66827
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change is to skip sending the MBP HOB since coreboot doesn't
use it and also helps to reduce the boot time by ~40msec on ADL-N.
Boot time data:
Before:
* 955:returning from FspSiliconInit 956,832 (110,268)
After:
* 955:returning from FspSiliconInit 944,528 (74,213)
BUG=b:241850107
TEST=Verified that boot time is reduced by ~40msec and also S0i3
is working.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I05d226fb5f05463341358cd20655f06376778bac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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This change is to skip sending the MBP HOB since coreboot doesn't
use it and also helps to reduce the boot time by ~40msec on ADL-N
variants.
Boot time data:
Before:
* 955:returning from FspSiliconInit 1,231,364 (117,051)
After:
* 955:returning from FspSiliconInit 1,198,221 (79,497)
BUG=b:241850107
TEST=Verified that boot time is reduced by ~40msec and also S0i3
is working.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Iaeaa8bcdf8467fdd467a10a98dd7582e8e0b067c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch adds the support to enable/disable skipping MBP HOB
from the devicetree based on mainboard requirement.
Only ADL-N FSP has the required support to skip the MBP HOB and
enabling it is saving the Boot time.
BUG=b:241850107
TEST=Build and boot to verify that the right value has been passed to
the FSP.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Iddeb2c652fac9513b14139d6f732d333bbb989d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The infrastructure for selecting an appropriate firmware image to use
the right descriptor is now ready so runtime descriptor updates are no
longer necessary. Since the different descriptor builds split along
HDMI/USB-C lines for nereid, a single VBT file can be used for each,
removing the need for runtime VBT selection as well.
BUG=b:229022567
TEST=Nereid type-C and HDMI outputs work as expected
Signed-off-by: Sam McNally <sammc@chromium.org>
Change-Id: Idf1fbd6c26203adbda002dec3f11e54a7b9f9b82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Change-Id: Id3367a708744d6a3ed0ba69ed8e0cafe0a5934b6
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Configure GPIOs in `mainboard_init()` instead of during FSP config.
Change-Id: Icc40ce71d2bd104c5f41e992f9b28824a3b734d6
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66169
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Split `gpio.h` into `gpio_early.c` for bootblock and `gpio.c` for
ramstage to match other System76 boards.
Change-Id: I24398ad459754ac80d92d70687ab70b22894a01c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This reverts commit feb551a92550fcc28b32aca77117aa743018b233.
Adding new variant "pazquel360" is not needed.
BUG=b:239599467
TEST=emerge-trogdor coreboot
Signed-off-by: chaogui@google.com
BRANCH=none
Change-Id: I4878d3a54f96fb9d38f2da1a1c918dfdef80a301
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66805
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DPTF Policy and temperature sensor values update from thermal team.
BUG=b:237640264
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I45b4f80cbec0723c63ac7fc7176e13ae5a2b54c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66365
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Debian 11 reports ´0:6:0 can´t derive routing for PCI INT D´.
Use FIXED_INT_PIRQ for INT D to PIRQ routing table.
BUG=NA
TEST=Boot Debian 11 on Siemens AS_TGL1 and verify no PIRQ error message
in ´dmesg´
Change-Id: If38c7b6f664e0f6533e583ce62504281a4092720
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch adds support for turning the PCIe SRCCLK# on and off during
RTD3 (just like the soc/intel/common/block/pcie/rtd3 driver).
TEST=GC6 and GCOFF sequences still work
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4b369cfcc7245a1c212fa65f65fdab542f60e196
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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For board revs 3 and later, the PG pin for the NVVDD VR moved from
GPP_E16 to GPP_E3. To accommodate this, the DSDT contains a Name that
this code will write the correct GPIO # to depending on the board rev,
and we'll use that instead.
BUG=b:239721380
TEST=still works on board rev 2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I11aec6069da8e086789419303871c6d0f5fb29af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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spm_set_power_control() is already called in spm_init(). It is not
necessary to call spm_set_power_control() again in the mtk_mcu reset
callback.
TEST=check SPM PC value (0x250) after SPM is loaded.
[INFO ] SPM: spm_init done in 54 msecs, spm pc = 0x250
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: I7ee517e1eb6485c52155a69d05781a61ddfe4cad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66785
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modify GPP_D17 setting for SD_WAKE_N.
BUG=b:242647845
TEST=Build and boot on pujjo
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Iacd89d27174869e34c48d1f62793ddc45b43f3f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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The DPTF power participant device needs to be notified when power
source changes so it can re-evaluate power source and power source
change count, this can be later used by DPTF along with methods
provided by EC.
Corresponding changes in EC are https://crrev.com/c/3545778 and
https://crrev.com/c/3547317
BUG=b:205928013
TEST=Build, boot brya0 and dump DSDT to check change
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I07f58b928a0dba92bec3817177142c586e5014b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Change-Id: I308dc7640e16b7cfb7679d81099d8896f3f454fc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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This is sort-of reverts commit cbf290c692b2 ("soc/amd/sabrina: drop
CPPC code"), since it turned out that the CPPC feature is supported
on Sabrina (now Mendocino) despite this being missing from the
documentation I looked at when writing the patch referenced above.
Since the CPPC ACPI code generation functionality has been moved to
common code, this isn't a direct revert.
BUG=b:237336330
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1c059653eeae207d723c77e8a78b19c86e362296
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This patch provides a mitigation path for having different size SPINOR
parts across Rex board revisions. Rex Proto 0 only has 64MB SPINOR
mounted on the board, and the plan is to use 32MB later with Proto 1
onwards.
Hence, the idea here is to maintain a 32MB SPI Flash layout across all
Rex board revisions, but the Proto 0 build only selects
BOARD_ROMSIZE_KB_65536 config for adding padding at the end of the
32MB range.
BUG=b:242825380
TEST=Able to create 64MB AP Firmware for Rex with below layout:
SI_ALL: 0-9MB
SI_BIOS: 9MB-32MB
Padding/Unused: 32MB-64MB
Additionally, able to hit CPU reset on MTLRVP (has 64MB SPINOR) with
Rex AP Firmware binary.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibcc2206456639ef4ff22e0c4069521e583be58cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66828
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This reverts commit eb80b1efa36c99e485b2604e913c2aa316168eea.
Reason for revert: Results into hard hang with serial debug msg inside FSP-S.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8e7cf804828da8939f591eb0770c8daf830c8d94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Currently, to enable/disable LTE based on fw_config on nissa, we have
two sets of GPIOs: lte_enable_pads and lte_disable_pads. This was to
prevent the SAR interrupt pin GPP_H19 from floating for the short period
of time between enabling it in gpio.c and disabling it in fw_config.c
(see CB:64270 for more details).
With the new pad-based GPIO overrides (CB:64712), this is no longer an
issue since the gpio.c and fw_config.c overrides are applied at the same
time. So simplify the LTE GPIO configuration by enabling all the LTE
pins in the variant gpio.c, then disabling them in fw_config.c if
needed.
BUG=b:231690996
TEST=LTE still works on nivviks
Change-Id: I5bf20a027414ea5e7c1f198d69e355c76f467244
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66776
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the SoC that was upstreamed as Sabrina was finally renamed to
Mendocino, also adjust the abbreviation used for the DXIO/DDI descriptor
struct array names.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I14ecf98e4a94376a70e783774c8f7b8701581220
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66815
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The flag EC_BATT_FLAG_CUT_OFF was added with the CL:
3704470: battery: Set battery cutoff flag
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3704470
This flag is set in the ACPI memory mapped area when the command
`ectool batterycutoff` is issued so ACPI code can respond
appriopriately. This CL adds the flags to coreboot ACPI.
BRANCH=none
BUG=b:217911928
TEST=Boot nipperkin with low & no battery
TEST=Boot skyrim with low & no battery
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I4e63ff4fc2d6b0ecf767a6bffd81f823c74c15bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66803
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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I added this header in commit a6c8b4becbd12fe6043557ca1e398c1a7c691007
(nb/intel/sandybridge: Rewrite get_FRQ). Relicense it as "BSD-3-Clause
OR GPL-2.0-or-later" and move it into the BSD-licensed commonlib part.
Change-Id: I89ebdcdf8d06e78e624e37a443696981b3b17b7d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66711
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the Shadow Registers from 2 through 5 and print information
from them accordingly. All values were taken from Intel document
number 571993.
Tested on the StarLite Mk III and the correct values are
shown:
[DEBUG] CSE: IBB Verification Result: PASS
[DEBUG] CSE: IBB Verification Done : YES
[DEBUG] CSE: Actual IBB Size : 88
[DEBUG] CSE: Verified Boot Valid : FAIL
[DEBUG] CSE: Verified Boot Test : NO
[DEBUG] CSE: FPF status : FUSED
Please note, the values shown are in an error state.
This replaces the Fuse check that is done via Heci, as this will only
work whilst the CSE is in a normal state.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8a9e7b329010fae1a2ed9c3fefc9765e617cdfe4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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coreboot is unable to disable certain devices, whilst many are hidden
DPTF and SMBus are not. Set this to enabled chipset so that it is
enabled by default.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I85d74179b6fe3c6126566422f82f7b806f80d0c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 0 (0000)
H58G56AK6BX069 2 (0010)
K3LKBKB0BM-MGCP 2 (0010)
BUG=b:242277219
BRANCH=None
TEST=run part_id_gen to generate SPD id
Change-Id: I46c168482113beb7cd28f387ed495847aba8602f
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Create the yaviks variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:242277219
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_YAVIKS
Change-Id: Id60fe0e54a8e0196a302141f58c6695779ac251a
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Build error for platforms using Intel FSP for TGL_IOT (FSP_TYPE_IOT). File FirmwareVersionInfoHob.h does not exist in Intel FSP TGL IOT package.
File FirmwareVersionInfoHob.h is included when DISPLAY_FSP_VERSION_INFO is enabled. Enable this config for non TGL_IOT only.
BUG = NA
TEST = Verify that DISPLAY_FSP_VERSION_INFO is disabled by default for TGL_IOT
configuration (Build Siemens AS_TGL1).
Change-Id: Ief5a7222daf6f1658e8dc04f97b4ddc2bcb74905
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66636
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Mendocino has more eSPI decode ranges than Picasso or Cezanne. To
support these additional ranges, introduce a new Kconfig option
SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES that can be selected by
the SoCs that support the additional eSPI IO/MMIO decode ranges.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib761cdf201c35805d68cf5e8e462607ffd9fa017
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Add GPIO configuration and device tree to enable the chip.
BUG=b:240607130
BRANCH=firmware-brya-14505.B
TEST=Patch linux with NXP's pending drivers
UWB device is probed and can respond to a simple hello packet
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I83be712d243c365a5cbfe6f69a6bd85440c5bec7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The patch updates the comments on return values and heci_reset()
triggering during error scenarios of heci_receive() and heci_send()
functions to reflect the current implementation.
Test=Build the code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I6c6c3312602c772147cb315db9ea1753d84a0fb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ib97d009c056b487136f20e5341b31183c65ef761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This wasn't done previously because not all files in the
src directory had the correct headers. Doing this earlier
would have broken the build.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ia6d7a7a17116e4c8e55354783085355fd45ff87a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66505
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to 8
- Set FastPkgCRampDisable VCCIA and VCCGT to 1
- Set pre-wake randomization time (DPA) to 100
BUG=b:241349500
TEST=build FW and checked fsp log.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Id4a1540de8c3ee74695631acc8181dcc446fe137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66783
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add FW_CONFIG probe based on pujjoteen boxster of below devices:
LTE, SD card, stylus, WFC camera, AUDIO
BUG=b:236158122
TEST=Boot to OS and verify that above devices are set based on
fw_cofnig.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I49fc5461e7affba68a6b89bf166c84598fbfa088
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66741
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Ghost has two amps and address are 0x3c and 0x3d.
BUG=b:231581723
BRANCH=firmware-brya-14505.B
TEST=max98396 driver can get the DSD property correctly.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I3b6a331ca42e97f984f3a585726c02452bb067f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Add MAX98396 support.
BUG=b:232606045
TEST=build passed.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I835b51ea1fcc9363992d43a625f80cb545802fc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Starting vboot earlier in bootblock instead of romstage is usually
preferred (smaller root of trust, among other things). Therefore
unselect VBOOT_STARTS_IN_ROMSTAGE for broadwell. Also remove the unused
BROADWELL_VBOOT_IN_BOOTBLOCK option.
Change-Id: If8feea403ee4cd3a16ed8cb0faf9f4ccb34feaaf
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This reverts commit f87489bbae5bb1ae3b17b6a03af9e309769b1f72.
Reason for revert: Broadwell actually supports early flash writes.
Change-Id: I342aefe464c72a32b41a40062b62d871caa0707b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The I2C config was unnecessarily placed in the overridetree. As we
prepare for fanout, this is going to cause unnecessary noisy changes.
Move the I2C config to the devicetree to avoid this.
BUG=None
TEST=Build
Change-Id: I09ad5c911a0fd00274761cb71e9b659b47cd6da1
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66802
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The PCIe spec explicitly states that the bottom-two bits of the next
offset are reserved for future use and should be masked. We can also
change the loop condition to avoid wrong offsets below 0x100 (exten-
ded capabilities always reside in the extended config space).
The whole patch series was tested on Google Samus and keeps the L1ss
configuration of the WiFi device in tact.
Change-Id: I0b622a0ce0a4a1127d266226ade0ec1e66e9fb79
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66459
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add some inline functions for the bit-wise operations, change the loop
body to an if-bail-out style and remove stateful variables.
Change-Id: Ia8db915f375737064e3486d313383d9b6c3eb2b8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66458
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Keeping these checks in generic code seems rather dangerous.
In theory, it could lead to endless loops even for compliant
devices, if we accidentally detect arbitrary register contents
as capability and use them as a pointer to another one. Not
to forget that the register reads can have side effects.
All users of this `cafe` have been converted to use
pciexp_find_ext_vendor_cap().
Change-Id: I70d21534e04282a4156572a290b83c46be085e0c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66456
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We have this quirk in our tree since the introduction of L1-substate
support[1]. The way we searched for this capability was rather crude:
We simply assumed that it would show up in the first data word of
another capability.
As it turned out that it is actually a proper vendor-specific capa-
bility that we are looking for, we can drop some of the mystic code.
This was confirmed to work on the device that was originally used
during development, Google/Samus.
[1] commit 31c6e632cf (PCIe: Add L1 Sub-State support.)
Change-Id: I886fb96e9a92387bc0e2a7feb746f7842cee5476
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Vendors can choose to add non-standard capabilities inside a
Vendor-Specific Extended Capability. These are identified by
the Extended Capability ID 0x0b.
Change-Id: Idd6dd0e98bd53b19077afdd4c402114578bec966
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Move the `offset` parameter into pciexp_find_extended_cap(). If it's
called with `0`, we start a new search. If it's an existing offset,
we continue the search.
This makes it easier to search for multiple occurences of a capa-
bility in a single loop.
Change-Id: I80115372a82523b90460d97f0fd0fa565c3f56cb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Now that we have functionality to get the minimal and nominal
frequencies, the corresponding fields in the CPPC config can now be
populated. If the HOB isn't present and/or the frequency values
could not be obtained, CPPC_UNSUPPORTED is still used; otherwise the
HOB-provided frequency in MHz is used for those two fields.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: Id3257690a3388d44ceceb7ac4f1db3d49e195caa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66551
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add common AMD FSP functionality to get the nominal and minimal CPU core
CPPC frequencies. Those functions will be used in the _CPC ACPI object
generation in a follow-up patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: I68ebdf610795d2673e0118a732f54f5f719b73c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66550
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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xhci.asl places the SS ports at 11-14, following HS ports 1-10. However,
for Nissa, the kernel detects 12 HS ports 1-12 and 4 SS ports at 13-16,
resulting in the PLD intended for SS ports 1 and 2 being associated with
HS ports 11 and 12.
Changing the asl for SS to 13-16 makes locations associate correctly and
peering work.
BUG=b:234544025
BRANCH=firmware-brya-14505.B
TEST=manually verified on Nissa and Brya devices
Change-Id: I57aef771a7ff086b71a9e90b81e1a3635f832b2f
Signed-off-by: Adam Mills <adamjmills@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66590
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The SMI sleep entry handler will access the SMN space via the index/data
register at PCI config space offsets 0xb8 and 0xbc of the device at bus
0, device 0, function 0. This register pair is also used by other
software components running on the x86 cores after boot, so it should be
saved and restored at the beginning/end of the SMI handler if it
accesses SMN. The sleep entry SMI handler is a special case, since the
OS is already done at the moment we enter the sleep SMI handler which is
the last code that gets run on the x86 cores before entering S3/4/5.
BUG=b:237004699
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0980562ef8a61489082a81c71d6d00d0786d68cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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EN_PP3300_EMMC will change to GPP_A21 to meet DP++ function and it based on Moli GPIO Table_20220803.xlsx. But it will let current eMMC skus can't boot into OS, so use the board_ver to decide which gpio table return and set override_gpio_table_id2 and early_gpio_table_id2 based on Moli GPIO Table_20220803.xlsx
1. set GPP_A21 to EN_PP3300_EMMC
2. set GPP_A22 to NC
3. set GPP_E20 to DDIC_DP_CTRCLK
4. set GPP_E21 to DDIC_DP_CTRLDATA
BUG=b:241370405
TEST=emerge-brask coreboot
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I0a2c8684d140738f43658cd6075ed083eee44e65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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This patch calls into a helper function to fill `2nd microcode loading
FSP UPD` if FSP is running CPU feature programming.
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8534305e4e973c975ad271b181a2ea767c840ae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66686
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the winterhold variant of the skyrim reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:240970782
BRANCH=None
TEST=util/abuild/abuild -p none -t google/skyrim -x -a
make sure the build includes GOOGLE_WINTERHOLD
Signed-off-by: Isaac Lee <isaaclee@google.com>
Change-Id: I0e16f0a674aa3f4687cd82d5840a3c2087148a51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66620
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit I73b7ddec50936f7836f915f459ca0bdc0777cb22.
Revert change to disable post codes. Post codes were initially disabled
because of an issue with initialization within the SMU.
BUG=b:227201571
TEST=Build and boot to OS in Skyrim.
Change-Id: I2a2bd2252a103c682b5d4ad5ecd1da42b3744083
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66092
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This board is no longer in the tree.
Change-Id: Ie4a626ce85fe0dc2b2d826dd8830a8e80ec331aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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By moving the large wait for FBVDD discharge from PGOF
to PGON, the whole time may be avoided if enough time has
elapsed between the successive calls.
BUG=b:239719056
TEST=With Nvidia test software, verify ACPI prints
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I891aa14f120d58c45b8965038a9d2f2a417b3f3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Now that the virtual wire situation is figured out, the GC6 sequence
is updated to match the latest HW design guide from Nvidia. This
allows Nvidia test software to (mostly) successfully execute the GC6
test, but with some PCIe AER errors.
BUG=b:214581763
TEST=tested with Nvidia test software
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia094c4fa9b4db094a59b9b6f02be1a649ee8569b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Since the VW GPIOs are not in the baseboard GPIO table, they do
not actually override anything, and hence do not actually get
programmed. This patch moves the programming from the ramstage
table to the bootblock table so they get programmed.
BUG=b:214581763
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I42db44d38df20dd2695921e2f252be163f6b17f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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It is highly unlikely that the "OEM revision" of the DSDT is 0x20110725
on mainboards with a chipset not yet released on 2011-07-25. Since this
comment is most likely to have been copy-pasted from other boards, drop
it from boards which use a chipset newer than Sandy/Ivy Bridge.
Change-Id: If2f61d09082806b461878a76b286204ae56bf0eb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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These comments don't add much value, so remove them.
Change-Id: I7e9692e3fe82345cb7ddcb11c32841c69768cd36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66713
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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This patch drops explicit usage of the address-of operator ('&') while
passing the function pointer (argument 0) to the
`mp_run_on_all_cpus` API.
Note: It's just cosmetic change without any real difference in the operation.
TEST=Able to build and boot Google/Kano where CPU feature programming
is successful on all logical processors.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2c77959a76d2240ad1bfb7a9d7b9db7e8aee42f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66685
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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If we already encountered the last extended capability in the
list, we'd call pciexp_get_ext_cap_offset() with `offset == 0`.
So it also needs to check if the passed offset is valid.
As there were no callers of pciexp_find_next_extended_cap()
yet, pciexp_get_ext_cap_offset() was only ever called with
`PCIE_EXT_CAP_OFFSET`.
Change-Id: I155c4691a34ff16661919913a3446fa915ac535e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Checking if the return value of the fsp_find_extension_hob_by_guid call
is NULL should make the code a bit easier to read.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6bdb07eab6da80f46c57f5d7b3c894b41ac23b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Different guybrush boards have different TPM IRQs. This change passes in
the correct GPIO to the TPM.
BUG=b:241824257
TEST=Boot guybrush and verify GPIO 3 was passed and that OEM Crypto test
passes
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I61954fa4493fd56e528b616ca65166a31917f557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The PSP currently uses a hard coded GPIO for the TPM IRQ. Not all board
versions use the same GPIO. This method allows the mainboard to pass
in the correct GPIO.
BUG=b:241824257
TEST=Boot guybrush and verify PSP message prints
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie05d095d7f141d6a526d08fbf25eb2652e96aa49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Since bootblock_soc_early_init gets called before
bootblock_mainboard_early_init which does the early GPIO setup, external
I2C level shifters that are controlled by GPIOs might not be enabled yet.
Moving the reset_i2c_peripherals call to bootblock_soc_init makes sure
that the early GPIO setup is already done when reset_i2c_peripherals is
called.
Haven't probed any SCL signal on the non-SoC side of the I2C level
shifters yet, but the waveform on the SCL pin of I2C3 on the SoC of a
barla/careena Chromebook doesn't have the longer than expected SCL
pulses any more.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If02140aef56ed6db7ecee24811724b5b24e54a91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Logo.bmp is overwritten with a custom one from coreboot. This needs to
be restored before the branch is updated otherwise git will report that
the repository is dirty.
Move this to the update recipe so that will always be done for any
recipe that needs to update the branch.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I85bf753a47d9e70d6555dec9a539e8ed7395bead
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66355
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust an ASCII art table so that it looks good: consistent padding and
aligned table borders.
Change-Id: I26196f969406e03f320256b0c3a337282f636914
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66707
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Steelix uses ps8640 for board revision < 2, and uses anx7625 for newer
revisions. So we use board_id to distinguish anx7625 and ps8640.
BUG=b:242018373
TEST=firmware bootsplash is shown on eDP panel of steelix.
Change-Id: Ia6907d2e6e290375946afb13176ab9a26dedd671
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
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BUG=b:232302324
TEST=Validated on qualcomm sc7280 development board
Observing 9th bit of skuid with below values,
1 means Modem device
0 means non-modem device
Signed-off-by: Venkat Thogaru <quic_thogaru@quicinc.com>
Change-Id: If62b272a43a4588f96e49c8b2b1d75862d401d31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Add support for SocInfo in coreboot. The API socinfo_modem_supported is
added to help to differentiate between LTE and WiFi SKUs.
BUG=b:232302324
TEST=Validate boards are detected correctly on LTE and Wifi SKUs
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: I61047ad49772c3796ba403cafde311ad184a4093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Add a new driver for NXP UWB SR1xx (e.g., SR150) device.
The driver was originally written by Tim Wawrzynczak as a WIP in
CL:3503703, and was based on drivers/spi/acpi.
BUG=b:240607130
BRANCH=firmware-brya-14505.B
TEST=On ghost (with follow-up CL), patch linux with NXP's pending
drivers
-> UWB device is probed and can respond to a simple hello
packet
Co-authored-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I5b1b0a5c1b48d0b09e7ab5f2ea6b6bc2fba2a7d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66466
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add OV 5675 MIPI camera to ghost, sensor eeprom, and IPU device to
device tree. Enable config for MIPI camera.
BUG=b:241343306
BRANCH=firmware-brya-14505.B
TEST=with ghost overlay changes, camera in camera app works
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: Ie079e43ae0f34efba396331922ea4a89eda72128
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This reverts commit 8b1c6c6cb384c89659abbd043c2566df358d8f95. With
updated APCB, eSPI configuration carries over to bootblock. Hence eSPI
does not need to be re-initialized in bootblock.
BUG=b:241426419
TEST=Build and boot to OS in Skyrim with PSP verstage.
Cq-Depend: chrome-internal:4929421
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I426b07329d4a0154d915381c99dcc9746b7a3d7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Introduce the `BROADWELL_LPDDR3` Kconfig option along with some wrapper
code to allow mainboards using LPDDR3 DRAM to supply the DQ/DQS maps to
chipset code without having to use `pei_data`. The only mainboard using
LPDDR3 is Google Samus.
Change-Id: I0aaf0ace243c03600430c2a7ab6389a7b20cb432
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55812
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Mainboards do not need to know about `pei_data` to tell northbridge code
where to find the SPD data. As done on Haswell, add the `mb_get_spd_map`
function and the `struct spd_info` type to retrieve SPD information from
mainboard code without having to use `pei_data` in said mainboard code.
Unlike Haswell MRC, Broadwell MRC uses all positions of the `spd_data`
array, not just the first. The placeholder SPD address for memory-down
seems to be different as well. Adapt the existing code to handle these
variations. Once complete, the abstraction layer for both MRC binaries
will have the same API.
Change-Id: I92a05003a319c354675368cae8e34980bd2f9e10
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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