mb/system76/gaze16: Split gpio.h into data files

Split `gpio.h` into `gpio_early.c` for bootblock and `gpio.c` for
ramstage to match other System76 boards.

Change-Id: I24398ad459754ac80d92d70687ab70b22894a01c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

8 files changed, 59 insertions, 28 deletions

diff --git a/src/mainboard/system76/gaze16/Makefile.inc b/src/mainboard/system76/gaze16/Makefile.inc
index 569eeb5228..6ade517c34 100644
--- a/src/mainboard/system76/gaze16/Makefile.inc
+++ b/src/mainboard/system76/gaze16/Makefile.inc
@@ -1,11 +1,13 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
 bootblock-y += bootblock.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
 
 romstage-y += variants/$(VARIANT_DIR)/romstage.c
 
 ramstage-y += ramstage.c
-ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
diff --git a/src/mainboard/system76/gaze16/bootblock.c b/src/mainboard/system76/gaze16/bootblock.c
index d25acdf383..0dc25dd200 100644
--- a/src/mainboard/system76/gaze16/bootblock.c
+++ b/src/mainboard/system76/gaze16/bootblock.c
@@ -5,5 +5,5 @@
 
 void bootblock_mainboard_init(void)
 {
-	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+	variant_configure_early_gpios();
 }
diff --git a/src/mainboard/system76/gaze16/include/variant/gpio.h b/src/mainboard/system76/gaze16/include/variant/gpio.h
new file mode 100644
index 0000000000..95d576294f
--- /dev/null
+++ b/src/mainboard/system76/gaze16/include/variant/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+
+#endif
diff --git a/src/mainboard/system76/gaze16/ramstage.c b/src/mainboard/system76/gaze16/ramstage.c
index cf374e381b..6963771d69 100644
--- a/src/mainboard/system76/gaze16/ramstage.c
+++ b/src/mainboard/system76/gaze16/ramstage.c
@@ -10,5 +10,5 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 
 	params->PchLegacyIoLowLatency = 1;
 
-	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+	variant_configure_gpios();
 }
diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3050/include/variant/gpio.h b/src/mainboard/system76/gaze16/variants/gaze16-3050/gpio.c
index a5e9b17f95..60b82de86f 100644
--- a/src/mainboard/system76/gaze16/variants/gaze16-3050/include/variant/gpio.h
+++ b/src/mainboard/system76/gaze16/variants/gaze16-3050/gpio.c
@@ -1,17 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
 #include <soc/gpio.h>
-
-static const struct pad_config early_gpio_table[] = {
-	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
-	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
-	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
-	PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH
-	PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
-};
+#include <variant/gpio.h>
 
 static const struct pad_config gpio_table[] = {
 	/* ------- GPIO Group GPD ------- */
@@ -285,4 +275,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_S7, NONE, DEEP), // DMIC_DAT_PCH
 };
 
-#endif /* VARIANT_GPIO_H */
+void variant_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3050/gpio_early.c b/src/mainboard/system76/gaze16/variants/gaze16-3050/gpio_early.c
new file mode 100644
index 0000000000..8c97e7f45e
--- /dev/null
+++ b/src/mainboard/system76/gaze16/variants/gaze16-3050/gpio_early.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+	PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
+};
+
+void variant_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3060/include/variant/gpio.h b/src/mainboard/system76/gaze16/variants/gaze16-3060/gpio.c
index f1d2cdabf5..ac14b64bf3 100644
--- a/src/mainboard/system76/gaze16/variants/gaze16-3060/include/variant/gpio.h
+++ b/src/mainboard/system76/gaze16/variants/gaze16-3060/gpio.c
@@ -1,17 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
 #include <soc/gpio.h>
-
-static const struct pad_config early_gpio_table[] = {
-	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
-	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
-	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
-	PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH
-	PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
-};
+#include <variant/gpio.h>
 
 static const struct pad_config gpio_table[] = {
 	/* ------- GPIO Group GPD ------- */
@@ -285,4 +275,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_S7, NONE, DEEP), // MIC_DATA_PCH
 };
 
-#endif /* VARIANT_GPIO_H */
+void variant_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3060/gpio_early.c b/src/mainboard/system76/gaze16/variants/gaze16-3060/gpio_early.c
new file mode 100644
index 0000000000..8c97e7f45e
--- /dev/null
+++ b/src/mainboard/system76/gaze16/variants/gaze16-3060/gpio_early.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+	PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
+};
+
+void variant_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}