diff options
| author | Tim Crawford <tcrawford@system76.com> | 2022-07-26 14:04:04 -0600 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-08-19 14:23:24 +0000 |
| commit | 3a5217a77b2561eb122d881581119753f2cd0039 (patch) | |
| tree | db86b34f6816a0147fdd68112e1dead75e7899ce | |
| parent | 34c8a19f9272c7483c4f6a009e59ef748625f25a (diff) | |
mb/system76/gaze16: Configure GPIOs in mainboard_init()
Configure GPIOs in `mainboard_init()` instead of during FSP config.
Change-Id: Icc40ce71d2bd104c5f41e992f9b28824a3b734d6
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66169
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
4 files changed, 13 insertions, 11 deletions
diff --git a/src/mainboard/system76/gaze16/ramstage.c b/src/mainboard/system76/gaze16/ramstage.c index 6963771d69..480c49c4d1 100644 --- a/src/mainboard/system76/gaze16/ramstage.c +++ b/src/mainboard/system76/gaze16/ramstage.c @@ -2,13 +2,12 @@ #include <soc/ramstage.h> #include <variant/gpio.h> -#include "variant.h" -void mainboard_silicon_init_params(FSP_S_CONFIG *params) +static void mainboard_init(void *chip_info) { - variant_silicon_init_params(params); - - params->PchLegacyIoLowLatency = 1; - variant_configure_gpios(); } + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/system76/gaze16/variant.h b/src/mainboard/system76/gaze16/variant.h index dcf2e38652..1f66112f5a 100644 --- a/src/mainboard/system76/gaze16/variant.h +++ b/src/mainboard/system76/gaze16/variant.h @@ -6,6 +6,5 @@ #include <fsp/soc_binding.h> void variant_memory_init_params(FSPM_UPD *mupd); -void variant_silicon_init_params(FSP_S_CONFIG *params); #endif diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3050/ramstage.c b/src/mainboard/system76/gaze16/variants/gaze16-3050/ramstage.c index 426ae84aaf..9d985630d0 100644 --- a/src/mainboard/system76/gaze16/variants/gaze16-3050/ramstage.c +++ b/src/mainboard/system76/gaze16/variants/gaze16-3050/ramstage.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "../../variant.h" +#include <soc/ramstage.h> -void variant_silicon_init_params(FSP_S_CONFIG *params) +void mainboard_silicon_init_params(FSP_S_CONFIG *params) { + params->PchLegacyIoLowLatency = 1; + // PEG0 Config params->CpuPcieRpAdvancedErrorReporting[0] = 0; params->CpuPcieRpLtrEnable[0] = 1; diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3060/ramstage.c b/src/mainboard/system76/gaze16/variants/gaze16-3060/ramstage.c index 7422613308..0f83461ae4 100644 --- a/src/mainboard/system76/gaze16/variants/gaze16-3060/ramstage.c +++ b/src/mainboard/system76/gaze16/variants/gaze16-3060/ramstage.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "../../variant.h" +#include <soc/ramstage.h> -void variant_silicon_init_params(FSP_S_CONFIG *params) +void mainboard_silicon_init_params(FSP_S_CONFIG *params) { + params->PchLegacyIoLowLatency = 1; + // PEG0 Config params->CpuPcieRpAdvancedErrorReporting[0] = 0; params->CpuPcieRpLtrEnable[0] = 1; |