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| author | V Sowmya <v.sowmya@intel.com> | 2022-08-17 20:02:11 +0530 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-08-21 14:54:38 +0000 |
| commit | 248708533b229254bde54290f01a72e58ab46da2 (patch) | |
| tree | e4133714420ee3c9c3e99633f1b5a6a2a7da11f0 | |
| parent | 6eda41743eec410f2f927ebe16844cbfa24b08bb (diff) | |
Revert "mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants"
This reverts commit 2b19d547c0866fef84bdb7b226ce7a4ac81af64f.
A power and performance analysis performed on Alder Lake demonstrated
that with an EPP (Energy Performance Preference) at 50% along with
EET (Energy Efficient Turbo) disabled, the overall SoC performance are
similar or better and the SoC uses less power.
For instance some browser benchmark results improved by 2% and some
multi-core tests by 4% while at the same time power consumption
lowered by approximately 7.6%.
BUG=b:240669428
TEST=verify that EPP is back to the by default 50% setting
`iotools rdmsr 0 0x774'
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I76d3914e51c5320af4c202558e1e7c57b7c0de54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree_m.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree_n.cb | 4 |
3 files changed, 0 insertions, 12 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 7afe27914f..f4e1fd97e1 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -170,10 +170,6 @@ chip soc/intel/alderlake register "cnvi_bt_audio_offload" = "true" - # set EPP to 45%: 45 * 256/100 = 115 = 0x73 - register "enable_energy_perf_pref" = "true" - register "energy_perf_pref_value" = "0x73" - # Intel Common SoC Config register "common_soc_config" = "{ .i2c[0] = { diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index deff4dc86d..4a41df61f7 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -143,10 +143,6 @@ chip soc/intel/alderlake register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" - # set EPP to 45%: 45 * 256/100 = 115 = 0x73 - register "enable_energy_perf_pref" = "true" - register "energy_perf_pref_value" = "0x73" - # Intel Common SoC Config register "common_soc_config" = "{ .gspi[1] = { diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index 0890649be3..ae9e11ec9b 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -116,10 +116,6 @@ chip soc/intel/alderlake register "cnvi_bt_audio_offload" = "true" - # set EPP to 45%: 45 * 256/100 = 115 = 0x73 - register "enable_energy_perf_pref" = "true" - register "energy_perf_pref_value" = "0x73" - # Intel Common SoC Config register "common_soc_config" = "{ .i2c[0] = { |