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2024-05-22soc/amd/phoenix/chip.h: add DDI configuration for openSILFelix Held
In the FSP case, the DDI descriptors aren't part of the devicetree and are instead retrieved in romstage by calling the mainboard's mainboard_get_dxio_ddi_descriptors function which allows updating the descriptors during romstage where the devicetree is static. In the openSIL case, the DDI configuration is first needed in ramstage, so we can put this info into the devicetree and update it if needed in ramstage. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3de12ff6af42e38751a3016efa313613677fa87a Reviewed-on: https://review.coreboot.org/c/coreboot/+/82580 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-22soc/amd/phoenix/chipset_*.cb: remove TODOFelix Held
Remove the TODO to update the chipset devicetree for Phoenix, since this has already been done. When re-checking the chipset devicetree, I found conflicting information about the existence of the PCI bridge to an external PCIe port on bus 0 device 1 function 5, but after looking into this, I'm reasonably certain that it either doesn't exist or at least wouldn't be usable, so I won't add that one to the chipset devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f0e1540ed45408e86186253d3982a7ba0065ac6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-05-21soc/intel/meteorlake: Add PsysPL2 configurationTony Huang
psys_pl2_watts is configured in SoC node of devicetree. Value represents Watts. BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot Change-Id: I9c4d62b93fc751db9e0ea04e475acb8861a844f8 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-16soc/intel/xeon_sp/gnr: Add IIO config utilsGang Chen
Add IIO configuration utils shared in GNR boards to handle the complex IIO configuration settings. Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690 Signed-off-by: Gang Chen <gang.c.chen@intel.com> Co-authored-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-15mb/amd/birman/devicetree_phoenix_opensil: add stub MPIO chipsFelix Held
Add the stub MPIO chips that contain the PCIe engine configuration for the external PCIe interfaces to the devicetree. Birman's port_descriptors_phoenix.c was used as a reference. The static configuration in the devicetree assumes that the default WLAN0_WWAN0 is selected; for the other cases we'll still need to fix up things accordingly in the mutable devicetree. The WLAN01 and WWAN01 cases still need to be handled in a follow-up patch. Since openSIL currently doesn't use the info from the gpio_group struct element, but deasserts both PCIe reset pins GPIO 26 and 27, the gpio_group isn't specified in the chip configuration in the devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icabe60322d46c1195284dd77ec39f9d143e3d2cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/81101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-14soc/intel/xeon_sp: Add Granite Rapids initial codesShuo Liu
coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single IO-APIC Xeon-SP platform. The same set of codes is also used for SRF (Sierra Forest) SoC. This patch initially sets the code set up as a build target with Granite Rapids N-1 FSP (src/vc/intel/fsp/fsp2_0/graniterapids). 1. All register definitions are forked from SPR (Sapphire Rapids) and EBG (Emmitsburg PCH)'s codes are reused. 2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later. Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Co-authored-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-14soc/intel/common: Add RPL tracehub supportAshish Kumar Mishra
Add PCI ID for RPL tracehub and update the PCI ID in the pci_device_ids[] in tracehub.c. Reference: Raptor Lake External Design Specification Volume 1 (640555) BUG=None TEST=Verified on brox Change-Id: I5d5c6c8ff44bcb5a7bbbd3e27a1577c169ecd6a9 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-05-14soc/intel/common: Add Panther Lake DIDsSaurabh Mishra
Reference: Panther Lake External Design Specification Volume 0.51 (815002) BUG=b:329787286 TEST=verified on Panther Lake Simics Platform. Change-Id: I941d6e1c8a697234b8e64a2523e60587897d7f7a Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81848 Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13soc/intel/xeon_sp: Use <spd.h>Elyes Haouas
Change-Id: Ib86df42c74474ab6d0bd389073c36ca0761748af Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-05-13soc/amd/common/block/psp: Comment unused symbolElyes Haouas
This adds a comment for unused AMD_FWM_POSITION_20000_DEFAULT. Change-Id: Id8369f488893e7e5b2e7e7126d1b53199ed1aa77 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-05-12soc/intel/lunarlake: Support stepping A0_2Saurabh Mishra
Details: - Add support for new Lunar Lake MCH ID 0x6410 - Add new CPU id 0xb06d1 Reference: Lunar Lake External Design Specification Volume 1 (734362) TEST=Build, boot the system and verfiy MCH-ID prints in bootblock stage. Below prints verified on Lunar Lake RVP board (lnlrvp). [DEBUG] MCH: device id 6410 (rev 02) is LunarLake M Change-Id: I976d7f269485633d835d204afa224736d71baaa8 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81847 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-12soc/intel/common: Add Lunar Lake CNVI device IDsSaurabh Mishra
Without this patch, ACPI SSDT does not supports and lists CNVW. With this patch, verified "CNVW" in ACPI SSDT listing. Scope (\_SB.PCI0) { Device (CNVW) { Name (_ADR, 0x0000000000140003) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Reference: Lunar Lake External Design Specification Volume 1 (734362) BUG=b:329787286 TEST=verified on Lunar Lake RVP board (lnlrvp). Change-Id: I5a0a3fbc9f43a6a573e33fcf3901055e10faaed1 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81846 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12vc/amd/opensil: introduce common mpio/chip.h header fileFelix Held
The chip drivers in the devicetree use the path where the corresponding chip.h file resides both to include this chip.h file in the static.c generated by util/sconfig from the devicetree and also for the names of the chip config and chip ops struct. To be able to build a SoC using either the MPIO chip driver from the openSIL stub or from the actual openSIL glue code without needing different devicetree files for the different cases, introduce a common MPIO chip.h file that then includes the correct MPIO header file. The chip config and ops structures also need to be renamed to take this change into account. Thanks to Matt for pointing out how to make the path to the actual MPIO chip.h file configurable via a Kconfig setting. This allows overriding this path from site-local without the need to have any reference to site-local in the upstream code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iead97d1727569ec0d23a2b9c4fd96daff4bebcf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82262 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-09mb/google/brox: Sending End of Post (EOP) asynchronouslyKarthikeyan Ramasubramanian
Currently EOP message is sent to CSE late in the boot flow. Instead send it asynchronously to save ~10 ms in boot time. BUG=b:337330958 TEST=Build Brox BIOS Image and boot to OS. Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-09soc/mediatek/mt8188: devapc: set devapc permission for MFGFei Yan
In order to support SVP Feature, EMI-MPU has to give MFG permissions to allow MFG to access secure buffer by secure read and write. Currently MFG is in domain 0, which include many other masters. Move MFG to domain 6. Set MFG remap, so that MFG can switch to protect mode by MFG register. Change MFG permission from NO_PROTECTION to SEC_RW_ONLY for domain 0, so that only AP in secure mode can access MFG_S_S-2 and MFG_S_S-5. BUG=b:313855815 TEST=emerge-geralt coreboot Change-Id: Ic6fb7d85bf9d4d92946a045a274b274abc440e1d Signed-off-by: Fei Yan <fei.yan@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-08soc/intel/xeon_sp/spr: Refine return value checksShuo Liu
mp_init_with_smm returns cb_err type, where 0 means success and negative values represent error (see cb_err.h). However, failure checks in form of "ret < 0" is not straightforward. Use "ret != CB_SUCCESS" instead. Change-Id: I7e57f2da0361f3109051e9a35b1cce81d559b261 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-07soc/intel/meteorlake: Determine TBT controllers exist by VID/DIDKane Chen
The original code uses TRE0-TRE3 register to determine whether or not the TBT controller exists. However, there is a remap in fsp could confuse the TRPx._STA. Ex: Disable TBT controller 0 on b:0 d:7 f:0 Enable TBT controller 1 on b:0 d:7 f:1 The FSP will do the remap and after the remap: TBT controller 1 is on b:0 d:7 f:0 TBT controller 0 is on b:0 d:7 f:1 This is becuase func 0 must exist per pci spec. However, the TRE0-TRE3 will not be remapped so that the ACPI TRPx._STA method could be confused. In such scenario, TRP0._STA will return 0x0, TRP1._STA will return 0xf which is wrong because TBT controller 1 is now at b:0 d:7 f:0 TEST=tested on rex and _TRPx._STA returns correctly. TBT function OK Change-Id: I54f2ea99cd1ec73dd0b71a6ba738aa927b0ae80f Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-07soc/intel/mtl: Fixed TBT PCIe devtree remappingKane Chen
The TBT PCIe devicetree settings are not remapped properly when TBT PCIe port 0 is disabled. This code refer SHA:58bc5d937 to remap the PCIe devtree settings properly in case of TBT PCIe port0 is disabled, TEST=Tested on screebo and found "Remapping PCIe Root Port #2 msg" showed up in coreboot log Change-Id: I7c7549ddf8ccdd67d7af7c69f51a84614cff9a03 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81841 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07device/dram/ddr{3,4}: Rename spd_raw_data for specific DDRElyes Haouas
Rename different spd_raw_data[] for DDR3 and DDR4. This is to solve the conflict when we include both "ddr3.h" and ddr4.h" for example here: src/device/dram/spd.c. Otherwise, it won't compile as DDR3 and DDR4 have different spd_raw_data[] size. Change-Id: I46597fe82790410fbb53d60e04b7fdffb7b0094a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07device/device_util: Add and use is_pci_bridge()Shuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: Ied4921f7dc7e144e580d05d4f2262777aa59d895 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81566 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07soc/intel/xeon_sp/spr: Print return codes for mp_init_with_smmShuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: Iee2234a3055fe8a94ecbfc820e9ff9e981f8dff2 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07soc/intel/xeon_sp/spr: Remove duplicated warningShuo Liu
When microcode is not found, intel_microcode_find() will output warning and skip the update. Remove the duplicated warning in CPU codes. TEST=Build and boot on intel/archercity CRB Change-Id: I0264edc01e90186a7b77d57f9c147d3b73747437 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07soc/intel/xeon_sp/spr: Add comments for get_thread_countShuo Liu
Add comments to clarify the usage of logical core count instead of physical core count. TEST=Build and boot on intel/archercity CRB Change-Id: I2bc94391f060cec9de91183021da03bc5c7438c0 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82097 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07soc/intel/xeon_sp/spr: Remove unused file includes in cpu.cShuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: I17b42331fa9b5f59d1fb1d66b9155c57e258357b Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82191 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06soc/intel/xeon_sp: Add fill_pd_distancesShuo Liu
Update a simple algorithm to cover some basic case for proximity domain distance handling. In the same time, the local variable usage of fill_pds() is optimized. TEST=Build and boot on intel/archercity CRB ACPI SRAT, SLIT and DMAR (Remapping Hardware Static Affinity) are generated correctly for 2S system. Change-Id: I2b666dc2a140d1bb1fdff9bc7b835d5cf5b4bbc5 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Ziang Wang <ziang.wang@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81442 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06common/block/tcss: Add config for PDC<->PMC mux configurationKrishna Prasad Bhat
Introduce a new Kconfig to enable PD controller to PMC mux configuration. Selecting this config enables direct communication from PDC to PMC. TCSS_HAS_USBC_OPS enables USB-C operations via the EC. When SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION is selected, disable TCSS_HAS_USBC_OPS to avoid sending PMC commands from AP/EC. BUG=b:332383540 TEST=USB3 plugged during G3, is detected after system boots from G3. Cq-Depend: chromium:5484387 Cq-Depend: chrome-internal:7106592 Change-Id: Ieeb503393418cdad43384be39ac49c93ba91e4db Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82077 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06soc/intel/xeon_sp/acpi: Refactor Xeon-SP ASL file locationShuo Liu
soc/intel/xeon_sp/acpi/*.asl are actually used only by SKX and CPX platforms and not forward compatible to later SoC generations. Move them to soc/intel/xeon_sp/acpi/gen1/ for clean maintenance. TEST=Build and boot on intel/archercity CRB Change-Id: Ib060b123ab0fd761f00d9a0573e9b73d600ea9ef Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82033 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06soc/amd/phoenix/include/platform_descriptor: remove TODOFelix Held
There's nothing in this header file that needs to be updated for the Phoenix SoC, so remove the 'Update for Phoenix' TODO. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9d7b5e8d8d6c8c22c2fae8e89d073481d21d8bdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/82150 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06block/fast_spi: Use read32p/write32p for SPI RWAshish Kumar Mishra
The current fast_spi code uses memcpy for rw. The SPI flash read/write has 4 byte limit, due to which the current 64 bit memcpy doesn't work. Hence update rw ops to use read32p/write32p. BUG=b:242829490 TEST=Verified MRC cache working on MTL 64-bit, future 64 bit platforms and RPL(brox/skolas) 32-bit platforms. Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-03soc/intel/xeon_sp/spr: Drop unused symbolElyes Haouas
SOC_INTEL_PCIE_64BIT_ALLOC is not used. Change-Id: I1ef52104ef1d883330b800215cb4d0475092d8fe Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-03soc/intel/xeon_sp: Remove unused xeonsp_acpi_create_madt_lapicsShuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: I06e5ff635c37253b1c8f151b62f696ff7e5e22ef Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82110 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-03mb/google/corsola: Initialize USB port 0Wentao Qin
The default MT8186 platform is to initialize USB3 port 1. Use option bit 27 in fw_config to enable initialization of USB2 port 0 to support devices mounted on it. BUG=b:335124437 TEST=boot to OS from USB-A boot to OS from SD Card BRANCH=corsola Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82089 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-02soc/ibm/power9/*: add file structure for SOCIgor Bagnucki
Boot device is stubbed to be able to build boards without errors. Change-Id: Ie74b1e34f9aebe151d0fdb0e95c003510fd864c3 Signed-off-by: Igor Bagnucki <bagnucki02@gmail.com> Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-02soc/intel/xeon_sp: Use fixed BDF for IBLShuo Liu
Integrated Boot Logic (IBL) codes doesn't support bootloader controlled Primary-to-Sideband Bridge (P2SB) hidden and unhidden. Hence, dynamically read IBL HPET/IOAPIC Bus:Device.Function (BDF) by bootloader is not supported, because when P2SB is hidden the register access is denied. TEST=Build and boot on intel/archercity CRB TEST=Build on intel/avenuecity CRB TEST=Build on intel/beechnutcity CRB Change-Id: I3975cb00e215c4984c63bb8510e8aef7d4cc85a4 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81321 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02soc/intel/xeon_sp: Move VPD based settings to mainboard codesShuo Liu
Configuration variable implementation (VPD, et al) is regarded to be mainboard specific and should not be bounded to SoC codes. This patch moves the VPD based settings (FSP log level, et al) from SoC codes to mainboard codes. TEST=Build and boot on intel/archercity CRB with no significant log differences Change-Id: Iefea72eec6e52f8d1ae2d10e1edbabdebf4dff91 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82090 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-02soc/intel/xeon_sp: Add get_cxl_modeShuo Liu
Configuration variable implementation (VPD, et al) is regarded to be mainboard specific and should not be bounded to SoC codes. Add get_cxl_mode so that SoC codes do not need to get this configuration from VPD any more. TEST=Build and boot on intel/archercity CRB with no significant log differences Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-02soc/intel/xeon_sp: Clean up device enablement configurationFelix Singer
Clean up by using is_devfn_enabled(). Change-Id: I9ea3d8b1b18e84a75a81a7e926d2c638766bb493 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82120 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02soc/intel/cannonlake: Clean up device enablement configurationFelix Singer
Clean up by using is_devfn_enabled(). Change-Id: I9a4984a096e72025e161bf117b70a7c59f2bb094 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82118 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02soc/intel/xeon_sp: Add device to proximity domain map utilsShuo Liu
In NUMA architecture, all devices (cpu, memory and PCI device) belong to specific proximity domain. Add utils to map device instance to their proximity domain. Proximity domain ID is the index assigned at the creation of proximity domains. There is no hard relationship between proximity domain ID and the device identities (e.g. socket ID). Hence we need the map utils to explicitly link them. For now the Sub-NUMA config isn't taken into account. TEST=Build and boot on intel/archercity CRB Change-Id: Icd14a98823491ccfc38473e44a26dddfbbcaa7c0 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Ziang Wang <ziang.wang@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81440 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-02soc/intel/xeon_sp: Make NUMA support by defaultShuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: I84f07c16e24e441a885144df8c805f1310acae29 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Ziang Wang <ziang.wang@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81439 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-30soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZEFelix Singer
Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total SPD size of 512 bytes. Set this as the default and remove the setting from mainboard Kconfigs. Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82115 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-29soc/intel/cmn/graphics: Make DDI-A 4 lanes configurableAngel Pons
As described in Intel document 336464 (8th gen S series datasheet volume 1), the CPU's 4 eDP lanes can be bifurcated, so that DDI-A (eDP) ends up with 2 lanes, and DDI-E (DP, typically used for VGA) has the remaining 2 lanes. This lets mainboards provide a VGA output without sacrificing one of the main 4-lane DDIs. Newer platforms seem to be lacking this. However, the way this is structured in coreboot does not allow boards to choose whether bifurcation should be enabled. Most boards in the tree do not use DDI-E (it doesn't exist on mobile platforms), but there are some boards (e.g. hp/280_g2) that use DDI-E and a DP-to-VGA converter chip to provide a VGA output. Replace `SOC_INTEL_CONFIGURE_DDI_A_4_LANES` with two new Kconfig options to allow boards to decide. Use `SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION` to specify whether a platform supports DDI-A bifurcation at all (do nothing otherwise, maintaining the original code's behaviour). If bifurcation is supported, the `SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION` is used to clear or set the `DDI_A_4_LANES` bit in the `DDI_BUF_CTL_A` register. Change-Id: I516538db77509209d371f3f49c920476e06b052f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82113 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-29include/device/pci_ids.h, soc/intel/mtl: add new MTL-P iGPU DIDMichał Kopeć
Found in a Clevo V560TU with Intel Core Ultra 155H Change-Id: I0f10808fd0e2d9c122743615fbce656c6d2447cc Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82071 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-29soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSPShuo Liu
In a server platform many silicon specific register lock operations are by default in FSP space. CHIPSET_LOCKDOWN_FSP provides an option to make sure the codes could be used out-of-box to build products. Change-Id: I8efcc1f27446be8e35f51e2568c4af6f8165486b Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82081 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-26soc/amd/genoa_poc/chip.h: remove empty newline before '}'Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7f18f2d754f24bfcc9cbf95a98fa6fe40aaf3b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-04-24soc/amd/common/amd_pci_util.h: assign 0 to PIN_A in pcie_swizzle_pinFelix Held
Explicitly assign a value of 0 to the first value of the pcie_swizzle_pin enum. This won't change the behavior, but clarifies that the actual values of the enum elements matter. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I21850e21f859f2079f804d4344a1a11856b27d90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-04-24soc/amd/common/amd_pci_util.h: rename bridge irq in pci_routing_infoFelix Held
Rename the 'irq' element of the pci_routing_info struct to 'bridge_irq' to better describe what it's doing. This struct element contains the number of the northbridge IOAPIC IRQ input the bridge IRQ is connected to signal power management or error reporting IRQs. Right now, coreboot doesn't put this information into the ACPI bytecode. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6410be673d15d6f9b5eb4c80b51fb705fec5b155 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-04-23soc/intel/alderlake: Add Twinlake graphics device IDsSowmya V
Add the graphics device IDs for Twinlake platform based on Platform External Design Specification. Document ID: 645548 BUG=b:326901448 TEST=Build tivviks and verify the IGD IDs. Change-Id: Ide008d5c5302bd589784bc917a2610c42a0fdee4 Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82038 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-22soc/amd/phoenix/acpi: call acpi_add_opensil_tables in openSIL caseFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifdfdbf193bd96a6dda72a2f23d51925fd369aa01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-04-22vc/amd/opensil/stub/ramstage: add acpi_add_opensil_tables stubFelix Held
In the non-stub openSIL coreboot glue code, this can be used to add the ALIB SSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3ccd2e81211417ad4ac94f208572e0fa4e1cf97c Reviewed-on: https://review.coreboot.org/c/coreboot/+/82012 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-22drivers/intel/fsp2_0: Introduce fsp print helper macrosAppukuttan V K
This patch introduces fsp print helper macros to print `efi_return_status_t' with the appropriate format. These macros are now used for fsp debug prints with return status efi_return_status_t is defined as UINT64 or UNIT32 based on the selected architecture BUG=b:329034258 TEST=Verified on Meteor Lake board (Rex) Change-Id: If6342c4d40c76b702351070e424797c21138a4a9 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81630 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-22device_util: Handle domain device in dev_get_domainShuo Liu
When the input device pointer pointing to a domain device, dev_get_domain returns the input device itself. TEST=Build and boot on intel/archercity CRB Change-Id: I3a278a8f573de95406ee256fba17767def4ad75d Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-19soc/amd/glinda: Add support for A0 and B0 steppingsAnand Vaikar
Update the A0 and B0 stepping IDs in CPU table per the PPR document 57254 Rev 1.56 and 1.69 Change-Id: I0072f25f981ac7d5df2522594c8788bfabcbf24c Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-18device/device_util: Rename dev_get_pci_domainShuo Liu
In coreboot, domain indicates hardware units that provide/group resource windows, For Xeon-SP, domains are PCIe compatible and further function in many aspects, e.g. PCIe, CXL, IOAT, UBOX. Rename dev_get_pci_domain to dev_get_domain to align with coreboot concept and distinguish from Xeon-SP concept. TEST=Build and boot on intel/archercity CRB Change-Id: I51b18b30fb41038869ea1384b01091da31a895b9 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-18device/device_util: Use const qualifierPatrick Rudolph
Allows to use the function in more places that expect the struct device to be readonly. TEST=Build and boot on intel/archercity CRB Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81275 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-16lynxpoint/broadwell: Correct L1 exit latency with ASPMAngel Pons
Lynx Point PCH reference code version 1.9.1 programs the larger L1 exit latency when ASPM is enabled. Document 535127 (BDW PCH-LP BS) also does the same. Correct the condition accordingly. On Lynx Point, also remove a now-redundant write to the LCAP register (offset 0x4c). Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57501 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-15soc/amd/picasso: Mark eMMC as non-removable for Windows 10/11 installCoolStar
Mark eMMC as non-removable to allow Windows 10/11 to install now that edk2 can boot from it. Change-Id: If0e14106521f99cb97d1bf421f4d82d1234c2f15 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-04-15src/mb: Rename new Makefile.inc files to Makefile.mkMartin Roth
These files were added after the switch. Change-Id: I1986e4f921e0e56fe5255433d4b9216dc7c4dc59 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81856 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-15soc/intel/xeon_sp/spr: Use official microcodesPatrick Rudolph
Use the official microcode updates from intel-microcode submodule by default. Downstream users can still decide to use their own files. Change-Id: I58121cc2ca7699d3d26581d7d5875ec74deeeb93 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81637 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-04-14soc/intel/broadwell: Add ACPI CIDs for SerialIO devicesAngel Pons
Lynxpoint has them, so add them on Broadwell as well. Change-Id: Iaa3e8044090262a64e58062ec4b116976978ce55 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-04-14lynxpoint/broadwell: Correct PCH-LP PCIe ASPM checkAngel Pons
Lynx Point PCH reference code version 1.9.1 checks bit 29 to detect ASPM on PCH-LP root port #6, not bit 28. Document 535127 (BDW PCH-LP BS) also uses bit 29 for root port #6. Correct the bit used in the check, as well as the surrounding comments. Change-Id: Ie4bd7cbbfc151762f29eab1326567f987b25ab19 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57500 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-14soc/intel/xeon_sp/spr: Drop microcode constraintsPatrick Rudolph
For current generation SPR/EMR you need to add at least 3 different microcodes having about 2MiB of size in total. This doesn't work with the hardcoded offset and size in Kconfig. Since it's loaded through FIT there's no need to pass it to FSP-T. Drop the hardcoded locations and place it somewhere in CBFS. Test: Booted on ibm/sbp1 with microcode confirmed loaded in bootblock on BSP. All the APs also have the correct microcode version loaded. TEST= Build and boot on intel/archercity CRB 'cat /proc/cpuinfo | grep microcode' result doesn't change before and after this patch. Change-Id: Iaa7007c2b11a860c9c664a7e753440bad7fe858e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81635 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Jincheng Li <jincheng.li@intel.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-04-14soc/intel/xeon_sp: Compress FSP-SPatrick Rudolph
Compress FSP-S to save some space in CBFS. Reduces the size of debug FSP-S by about 25%. Test: Still boots on ibm/sbp1. TEST= Build and boot on intel/archercity CRB. Change-Id: I6248e7cabbce45f6c2fedfab34f328309f87e868 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81634 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-04-13soc/intel/broadwell/pch/sata.c: Add missing SATA init stepsAngel Pons
WildcatPoint-LP BIOS spec lists them, and are the same for Lynxpoint. Change-Id: Iba28c1591affafeb37097084c2fa58128974bd00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-13sandybridge,haswell,broadwell: Use DIV_ROUND_CLOSEST macroAngel Pons
Integer division in C truncates toward zero. When the dividend and the divisor are positive, one can add half of the divisor to the dividend to round the division result towards the closest integer. We already have a macro in commonlib to do just that, so put it to good use. Tested with BUILD_TIMELESS=1, coreboot images for the Asus P8Z77-V LX2 and the Asrock B85M Pro4 do not change. Change-Id: I251af82da15049a3a2aa6ea712ae8c9fe859caf6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52651 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12tree: Drop duplicated <device/pci_{def,type}.h>Elyes Haouas
<device/pci.h> is supposed to provide <device/pci_{def,type}.h> Change-Id: Ia645b8dba8c688187a25916f508593f333821f88 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81831 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12tree: Drop duplicated <device/{path,resource}.h>Elyes Haouas
<device/device.h> is supposed to provide <device/{path,resource}.h> Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-12tree: Drop unused <cbmem.h>Elyes Haouas
Change-Id: If8be8dc26f2729f55dc6716e6d01e2b801d79e44 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-11tree: Drop unused <timestamp.h>Elyes Haouas
Change-Id: Ic690a7543f8a1e072650917d7a1e9e3b9dc371a3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-04-11tree: Drop unused <timer.h>Elyes Haouas
Change-Id: Ib454330c5f584760c47ff0127a720cec5773b922 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-04-11tree: Drop unused <edid.h>Elyes Haouas
Change-Id: I66265727b68b6ad10722439314b466298dbfff28 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81821 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-11tree: Drop unused <halt.h>Elyes Haouas
Change-Id: Icd00f30a96c53f70babdcb8a77c4b6c2868619d8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-11tree: Drop unused <stdlib.h>Elyes Haouas
Change-Id: Ie7e36cfa5a09d94bb58f12f9bd262255a630424c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81819 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-11tree: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-11soc/intel/alderlake: Support missing CLKREQ workaround on RaptorLake FSPBenjamin Doron
IoT variants of the RaptorLake FSP support the `PchPciePowerGating` and `PchPcieClockGating` UPDs, so, remove the preprocessor check that only enabled it for AlderLake FSPs. Change-Id: I583a4b257b72f992fdb6390d00e187d04a749177 Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81803 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-11soc/intel/**/fast_spi.c: Reorganize some statementsAngel Pons
Avoid calling `acpi_device_scope()` and `fast_spi_acpi_hid()` if the result won't be used. Also, reorder a condition so that compile-time constants appear first, so as to help the compiler optimize it out. Change-Id: I42ce55c2978ad9c593c359c5decd5842fb3a97a1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-04-11tree: Drop unused <string.h>Elyes Haouas
Change-Id: I0e216cbc4acf9571c65c345a1764e74485f89438 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81818 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-10soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0Shuo Liu
MAINBOARD_USES_FSP2_0 selects PLATFORM_USES_FSP2_0 and POSTCAR_STAGE which are used by all Xeon-SP platforms. After the removal of MAINBOARD_USES_FSP2_0, PLATFORM_USES_FSP2_0 is implicitly selected by SoC Kconfigs in PLATFORM_USES_FSP2_X, POSTCAR_STAGE is selected by XEON_SP_COMMON_BASE. TEST=Build and boot on intel/archercity CRB Change-Id: I45332d49dd21f9749fce458877777a4b783a1b11 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81783 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-10tree: Drop unused <elog.h>Elyes Haouas
Change-Id: I40e2e5a786499abbe2fce63d6e0f1ac1e780ab51 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-10tree: Drop unused <stdio.h>Elyes Haouas
Change-Id: I26c2abfce3417ed096d945745770fcae91a1e4ad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81814 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-09tree: Drop unused <post.h>Elyes Haouas
Change-Id: Ic7f6690786661e523292f7382df71ae4ad04d593 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-04-09soc/intel/alderlake: Fix non-local header treated as localElyes Haouas
Change-Id: I93e6989633b9ac1b2738b812e3f8b442ecfdcbf0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81813 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09tree: Drop unused <delay.h>Elyes Haouas
Change-Id: I265e427254ce9f735e65b0631c43f98bc778a34f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81812 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-09tree: Drop unused <console/console.h>Elyes Haouas
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09soc/intel/xeon_sp: Add iio_ioapic.cShuo Liu
Move the soc_get_ioapic_info for platforms with IIO IO-APICs to a separate file from src/soc/intel/xeon_sp/acpi.c. TEST=Build intel/archerticy CRB Change-Id: I59022b7685539491604724ef3b550da1cfd53f13 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-04-09soc/samsung: Move 'inline' between storage class and typeElyes Haouas
Change-Id: Iccdb4770890751b7f9d1b35248fe57993342fd50 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-09soc/mediatek/common/include/soc: Include header file for check_memberRuihai Zhou
To fix the build error below when include i2c_common.h, we should include the necessary header for check_member. """ src/soc/mediatek/common/include/soc/i2c_common.h:24:42: error: expected ')' before numeric constant 24 | check_member(mt_i2c_dma_regs, dma_tx_len, 0x24); | ^~~~~ | ) """ TEST=abuild -t google/geralt -b ciri -a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I266571686e452e2b7514afee42ff0a48f8891831 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81684 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-07soc/amd/genoa_poc: Allow using UART with DEBUG_SMI=yBenjamin Doron
When DEBUG_SMI is selected, common code may use these helpers to handle addressing and initialising the SoC-specific UART. Therefore, add uart.c to be compiled into SMM. Change-Id: If7c6f2346d5f9ffb371d51d1de6f0b695acedf10 Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81072 Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-06lib: Refactor bmp_load_logo() implementationSubrata Banik
This refactoring ensures bmp_load_logo() takes logo_size as an argument, returning a valid logo_ptr only if logo_size is non-zero. This prevents potential errors from mismatched size assumption. BUG=b:242829490 TEST=google/rex0 builds successfully. Change-Id: I14bc54670a67980ec93bc366b274832d1f959e50 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81618 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-04-05soc/intel/xeon_sp: Share unlock_pam_regions()Shuo Liu
unlock_pam_regions() is needed for SKX and CPX. Put the codes into chip_gen1.c so that it could be shared among SoC generations. After shared, unlock_pam_regions() is still called from SKX and CPX SoC specific codes. SPR will also use chip_gen1.c, but it will not call unlock_pam_regions(). TEST=Build and boot on intel/archercity CRB Change-Id: Idbc7dc6dd22a1747a65543666fc714a0872e6b37 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-04-04soc/intel/common/block/fast_spi: probe for 2nd flash componentMichał Żygowski
Fast SPI code assumes only one SPI flash is present. The SPI flash driver for older southbridges is able to detect multichip. See the spi_is_multichip() in src/southbridge/intel/common/spi.c. Some boards (e.g. Lenovo ThinkCentre M920 Tiny) still come with two chips populated instead of one. With this change, both chips are probed, and the correct total size is calculated. Otherwise, only the first one was probed, which resulted in an error such as: SF size 0x1000000 does not correspond to CONFIG_ROM_SIZE 0x1800000!! Change-Id: I8d7449f9e1470dc234fe5ba5217d3ce4c142b49c Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-04tree: Remove duplicated <stdint.h>Elyes Haouas
<types.h> is supposed to provide <stdint.h>. Change-Id: Ia68a0dc8fba4a48401e213ebb8356e32f0a019ab Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-04-04soc/intel/cache_as_ram_fsp.S: Drop unused preprocessing directivesArthur Heymans
Change-Id: I42bb15b8534d16401cd06ff803a8425221c5f3c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-04-04drivers/intel/fsp2_0: Support FSP-T in long modeArthur Heymans
Call into FSP-T using the protected mode wrapper and enter long mode in FSP-T support assembly code. TEST: Booted on ibm/sbp1 in long mode. Change-Id: Id6b9780b06b4bfbb952e32091ffbf3d0014f2090 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-04soc/intel/xeon_sp: Use default soc_get_ioapic_infoShuo Liu
intel/common/block/acpi provides default soc_get_ioapic_info for single IOAPIC model. Use the default soc_get_ioapic_info when XEON_SP_HAVE_IIO_IOAPIC is not set. This model fits for SPR and later. TEST=Build and boot on intel/archercity CRB Change-Id: I1ecfba49cd9b4dfbb3f11d58d04d07ea1752a131 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-04-03cpu/x86/topology: Add node ID parserPatrick Rudolph
Currently the SRAT table only exposes one proximity group as it uses the LAPIC node_id, which is always initialized to 0. Use CPUID leaf 0x1f or 0xb to gather the node ID and fill it to make sure that at least one proximity group for every socket is advertised. For now the SNC config isn't taken into account. Change-Id: Ia3ed1e5923aa18ca7619b32cde491fdb4da0fa0d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-04-01soc/intel/xeon_sp: Remove PAM unlock operationsShuo Liu
unlock_pam_regions routes Programmable Attribute Map (PAM) access to DRAM. In SPR, PAM routing to DRAM is covered by FSP. Move the step to SoC specific codes. TEST=intel/archercity CRB Change-Id: I3fd1d806807449e6a4d9d4d2c8a47ce61ed53018 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-01intel/common/pch: Add Kconfig SOC_INTEL_COMMON_IBL_BASEShuo Liu
IBL (Integrated Boot Logic) provides a subset of server PCH logics for no-PCH solution. IBL is with limited features and registers exposed, PCIe root ports/USB/SATA/LAN support are removed. Change-Id: I8f3d64a2dd3b79ec5a9e4306f40b012b00387259 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81314 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-01soc/intel/xeon_sp: Redefine data types for GNRShuo Liu
Granite Rapids (6th Gen Xeon-SP) FSP introduces UDS_STACK_RES/ UDS_SOCKET_RES and retires the usages of STACK_RES/ IIO_RESOURCE_INSTANCE. Make redinitions to make Xeon-SP common codes to work for both 6th Gen before and later. Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81040 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-01soc/intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPLKilari Raasi
The RPL FSP currently uses HECI commands to retrieve the chipset initialization version because the MBP HOB creation is disabled (SkipMbpHob=1). This has resulted in an approximate 150ms increase in boot time. Investigations are ongoing to determine the cause of the delay when using HECI commands. As an interim solution, this patch sets SkipMbpHob=0, enabling the use of MBP HOB or acquiring the chipset initialization version, which is expected to reduce the boot time. BUG=b:328430167 TEST= Able to build,boot and collect boot time data of brya. With this patch: 963:returning from FspMultiPhaseSiInit 1,337,481 (249,046) Without this patch: 963:returning from FspMultiPhaseSiInit 1,496,268 (408,194) Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Change-Id: I8a99a57b644732074e41051d99e63576f1edd229 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 03:58:14 +0000