diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2024-05-12 11:30:35 +0200 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2024-05-13 17:12:19 +0000 |
| commit | c2837e70b9171886c9efdc4ae9b089b1fe2732d3 (patch) | |
| tree | 193fced2667375e707bf55ac7c119423d64c6dac /src/soc | |
| parent | 27becf5da6a6b61de165013e0680265a6f6fbfbb (diff) | |
soc/intel/xeon_sp: Use <spd.h>
Change-Id: Ib86df42c74474ab6d0bd389073c36ca0761748af
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/ddr.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/romstage.c | 3 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/ddr.h b/src/soc/intel/xeon_sp/include/soc/ddr.h index bb10caaf1f..0b5bdb6b15 100644 --- a/src/soc/intel/xeon_sp/include/soc/ddr.h +++ b/src/soc/intel/xeon_sp/include/soc/ddr.h @@ -9,7 +9,6 @@ * currently DDR4 only supports 1.2V, DDR5 only supports 1.1V. */ #define SPD_VDD_DDR4 3 #define SPD_VDD_DDR5 0 -#define SPD_TYPE_DDR5 0x12 /* DDR_*_TCK_MIN are in picoseconds */ #define DDR_800_TCK_MIN 2500 diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index bdb9886a8d..c339506573 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -13,6 +13,7 @@ #include <fsp/util.h> #include <hob_iiouds.h> #include <hob_memmap.h> +#include <spd.h> #include <soc/chip_common.h> #include <soc/romstage.h> #include <soc/pci_devs.h> @@ -330,7 +331,7 @@ void save_dimm_info(void) dest_dimm->soc_num = soc; - if (hob->DramType == SPD_TYPE_DDR5) { + if (hob->DramType == SPD_MEMORY_TYPE_DDR5_SDRAM) { /* hard-coded memory device type as DDR5 */ mem_dev_type = 0x22; data_width = 64; |