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authorSaurabh Mishra <mishra.saurabh@intel.com>2024-04-12 19:37:20 +0530
committerMartin L Roth <gaumless@gmail.com>2024-05-12 18:57:05 +0000
commit7f2020b7127a1f1a88c75a7bde11b24c9daec5a8 (patch)
tree0e3f284fed3b50ed7ceea56c3e4802dd7dc2abfb /src/soc
parent83fd2d8a284c77bcb87007e62c4658b264983ff8 (diff)
soc/intel/common: Add Lunar Lake CNVI device IDs
Without this patch, ACPI SSDT does not supports and lists CNVW. With this patch, verified "CNVW" in ACPI SSDT listing. Scope (\_SB.PCI0) { Device (CNVW) { Name (_ADR, 0x0000000000140003) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Reference: Lunar Lake External Design Specification Volume 1 (734362) BUG=b:329787286 TEST=verified on Lunar Lake RVP board (lnlrvp). Change-Id: I5a0a3fbc9f43a6a573e33fcf3901055e10faaed1 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81846 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/common/block/cnvi/cnvi.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index fed95492f7..98642dc45d 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -21,6 +21,10 @@ static struct device_operations cnvi_wifi_ops = {
};
static const unsigned short wifi_pci_device_ids[] = {
+ PCI_DID_INTEL_LNL_CNVI_WIFI_0,
+ PCI_DID_INTEL_LNL_CNVI_WIFI_1,
+ PCI_DID_INTEL_LNL_CNVI_WIFI_2,
+ PCI_DID_INTEL_LNL_CNVI_WIFI_3,
PCI_DID_INTEL_MTL_CNVI_WIFI_0,
PCI_DID_INTEL_MTL_CNVI_WIFI_1,
PCI_DID_INTEL_MTL_CNVI_WIFI_2,