summaryrefslogtreecommitdiff
path: root/src/soc/mediatek/mt8195/Makefile.inc
AgeCommit message (Collapse)Author
2022-07-06soc/mediatek: Move some gpio functions to common/gpio_op.cRex-BC Chen
gpio_set_pull(), gpio_set_pull_pu_pd() and gpio_set_spec_pull_pupd() can be reused for mt8192, mt8195 and mt8186, so move it to new file "gpio_op.c" in common folder. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I81ab9b01ee20fccf3ef29c5902597b5045d3e36a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65641 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06soc/mediatek: Make timer_prepare() a common functionRex-BC Chen
timer_prepare() is the same for MT8195 and MT8186, so move it to common folder. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I91a6f4ecc665a058cb7a0ba96c15b27d6dc97d13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65602 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06soc/mediatek: Move wdt_set_req() to common folderBo-Chen Chen
There are more and more variables which are SoC-specific, so add soc/wdt.h for each SoC and rename common/wdt.h to common/wdt_common.h. wdt_set_req() is almost the same for mt8192, mt8195 and mt8186, so move it to a common file wdt_req.c. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I7a334b3e7cd4f24a848dd31aca546dc7236d5fb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65636 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-24soc/mediatek: Clean up Makefile.inc for mt8186, mt8192 and mt8195Yidi Lin
Clean up Makefile.inc by sorting entries and moving common entries to all-y. In this way it is more clear to know what drivers have been involved in each stage and the hardware differences between each SoC. BUG=none TEST=emerge-corsola coreboot TEST=emerge-asurada coreboot TEST=emerge-cherry coreboot Change-Id: Idfc7de36ebf36650f7c6bd1584ef77e2a540cde9 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65315 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-29mb/google/cherry: Pre-initialize PCIe at the bootblock stageJianjun Wang
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be delayed 100ms (TPVPERL) for the power and clock to become stable. Instead of asserting PERST# right before PCIe initialization and waiting for 100ms, which is currently the only function of 'mtk_pcie_pre_init', so that the extra 100ms delay in ramstage is avoided. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29soc/mediatek/mt8195: Add early init supportJianjun Wang
Add early init support for MT8195 platform. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I4eb7da53ff76c385cab18bbf84970e96b61662ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/63020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-10soc/mediatek/mt8195: Add driver to configure PCIeJianjun Wang
Add a new function 'mtk_pcie_pre_init' to assert the PCIe reset at early stage to reduce the impact of 100ms delay. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: If6799c53b03a33be91157ea088d829beb4272976 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-14soc/mediatek: add support for tracker version oneRex-BC Chen
There are two versions for tracker system: Version 1 for MT8186, and version 2 for MT8192 and MT8195. Reference document: MT8169_bus_dbg_tracker_cfg_reg.xls from MediaTek internal. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Idb146974da118b1cf5a349370bf7b2fa13f1aba8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59989 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-29soc/mediatek: move bustracker_init before watchdog resets againRex-BC Chen
The checking register will be cleared after EC resets, so we move bustracker dump from ramstage to bootblock, before triggering EC reset. TEST=bustracker shows status before watchdog resets BUG=b:207743045 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic18dc9742cd9f657a035a374e28371dfc5f04ac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17soc/mediatek: move MSDC drivers to soc folderRex-BC Chen
Setting of MSDC is defined by soc, so we move them to soc folder. TEST=emerge-cherry coreboot; emerge-asurada coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I84ad8a4cde120c97024870ebf750d44b36c2284d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek: move functions of mmu operation to common folderRex-BC Chen
Move mtk_soc_disable_l2c_sram and mtk_soc_after_dram to common folder which are the same between MT8192, MT8195 and MT8186. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I8f49214b932a8d28ed2ca0d764dc745fa8ad330d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-12soc/mediatek/mt8195: Add APU device apc driverFlora Fu
Add APU device apc driver and set up permissions. APU has its own device apc for control access by domains. For Domain 0, the access to the following slaves are restricted to security read and write: apusys_ao-2, apusys_ao-4, apusys_ao-5, apu_sctrl_reviser, apu_iommu0_r1 apu_iommu0_r2, apu_iommu0_r3, apu_iommu0_r4 apu_iommu1_r1, apu_iommu1_r2, apu_iommu1_r3,apu_iommu1_r4 For VPU, D0/D5 are set as no protection, other domains are forbidden. For other slaves, the D0 is no protection, other domains are forbidden. BUG=b:203145462 BRANCH=cherry TEST=boot cherry, check dump log and test permissions Signed-off-by: Flora Fu <flora.fu@mediatek.com> Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-03soc/mediatek: Add an overridable function for WDT clear statusRex-BC Chen
mtk_wdt_clr_status is different for MT8186 and MT8195, so we move this function to soc folder. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia8697ffdca1e2d1443f2259713c4ab6fdf1b1a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58834 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek/mt8195: add apusys init flowFlora Fu
Set up APU mbox's functional configuration registers. BUG=b:203145462 BRANCH=cherry TEST=boot cherry correctly Signed-off-by: Flora Fu <flora.fu@mediatek.com> Change-Id: I5053d5e1f1c2286c9dce280ff83e8b8611b573b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58794 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-13soc/mediatek/mt8195: add tracker dumpZhenguo Li
Tracker is a debugging tool, include AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. Signed-off-by: Zhenguo Li <ot_zhenguo.li@mediatek.corp-partner.google.com> Change-Id: If457f4a096cd63038bf6b40552aa3caaba33d5fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58243 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29soc/mediatek/mt8195: initialize DFDRex-BC Chen
DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values could be showed for debugging. BUG=b:192429713 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507c99b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57980 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08mb/google/cherry: Fix incorrect timestamps in eventlogChen-Tsung Hsieh
The eventlog requires RTC to provide correct timestamps, so we have to turn on the config and add the common drivers. BUG=b:199003609 TEST=check timestamp in 'mosys eventlog list' BRANCH=none Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org> Change-Id: Ia382cd023fcbfdf2c1efeb7b32c0b99feb71effa Reviewed-on: https://review.coreboot.org/c/coreboot/+/57403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-23soc/mediatek/mt8195: add HDMI low power settingRex-BC Chen
Add HDMI low power setting to reduce power consumption. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ica91645789e5de3401131e7050d2b1ee06c535dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/57042 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09mb/google/cherry: select mmc storage configWenbin Mei
Select mmc storage config for cherry. BUG=b:195274787 TEST=emerge-cherry coreboot BRANCH=cherry Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I67c8795b6e6fc121e8fe61c40da05593faa02d94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-04soc/mediatek/mt8195: Add devapc basic driversNina Wu
Add basic devapc (device access permission control) drivers. DAPC driver is used to set up bus fabric security and data protection among hardwares. DAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DAPC driver. 1. Initialize devapc. 2. Set master domain and secure side band. 3. Set domain remap. 4. Set default permission. Change-Id: I3677657a117caed0d73526f78b0ebe8180148335 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-24soc/mediatek/mt8195: Support 4 channel DRAM in DPM init flowRyan Chuang
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: If2e9d8a4dcfad28c48a2b5fa7c92f70fae879e67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-23soc/mediatek/mt8195: Add DPM firmware filesRyan Chuang
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I51e8ebf5a75ac629bed51665e12bafa740b4b81d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-23soc/mediatek/mt8195: Add mt6360 driver for PMIC accessAndrew SH Cheng
Signed-off-by: Andrew SH Cheng <andrew-sh.cheng@mediatek.com> Change-Id: Ieaf234f35f2b7d440bdf1e6ec4c455af7b311623 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55710 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18soc/mediatek/mt8195: add mt6691 driverhenryc.chen
Add mt6691 buck control for DRAM to run fast calibration test. It is needed to get and set voltage during testing. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Change-Id: I4fb9f7245d44383a6a3a0cf8d00f7f503cbdeb06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55575 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18soc/mediatek/mt8195: add eDP supportJitao Shi
BUG=b:189985956 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I37326ad053295aa4944c8291e4e7a7d69c8f3f63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55573 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16soc/mediatek/mt8195: Add ddp driver to support eDP outputjason-jh.lin
Add ddp (display controller) driver that supports overlay, read/write DMA, etc. The output goes to display interface DP_INTF0 directly. Add ddp gclast and output_clamp settings on mt8195 to support multi-layer display. BUG=b:189985956 Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> Change-Id: I9d5dd1025c4766218c2b1d86b9b1f97f2eab53d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55509 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10soc/mediatek/mt8195: add power and power control for eDPJitao Shi
1. Add API of TVD_PLL1 mt_pll_set_tvd_pll1_freq() for setting rate. 2. Add API of TVD_PLL1 edp_mux_set_sel() for mux sel. 3. Add eDP power domain control. BUG=b:189985956 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I9e43e0ffeb7b8bcd1786a8d2f5acbf22d5ab501f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55346 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-05soc/mediatek/mt8195: Enable mt8195 auxadcZhiqiang Ma
Enable auxadc on MediaTek mt8195 platform. Signed-off-by: Zhiqiang Ma <zhiqiang.ma@mediatek.com> Change-Id: Ie79420e20c9ed6155791b490e1b5e4b44a579a49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-04soc/mediatek/mt8195: add SPM loaderDawei Chien
This patch adds support for loading SPM firmware from CBFS to SPM SRAM. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. TEST=program counter of SPM is correct value after booting up. Change-Id: Ia0f9b9f86e44b293c1cc47213946304c64aea75e Signed-off-by: Dawei Chien <dawei.chien@mediatek.com> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55140 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-03soc/mediatek: Initialize SSPMRex-BC Chen
Load SSPM firmware and boot up SSPM in ramstage. This adds 23ms to the boot time. TEST=Load SSPM blob ok, and we can see some logs of SSPM from AP. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-26soc/mediatek/mt8195: Initialize MCUPMalex.miao
Load MCUPM firmware and boot up MCUPM in ramstage. TEST=can see MCUPM log from AP console Signed-off-by: alex.miao <alex.miao@mediatek.corp-partner.google.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I9e8c45ce7166644b94319ec2e7836d3d3c8008dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/54899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-18soc/mediatek/mt8195: enable ARM64_USE_ARM_TRUSTED_FIRMWAREYidi Lin
Enable ATF configuration to support multi-core. TEST=boot to kernel with multi-core support. BUG=b:177593590 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Id1ef29894fa3a6022574c3874dee62617133b12c Reviewed-on: https://review.coreboot.org/c/coreboot/+/53898 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14soc/mediatek/mt8195: Initialize DRAM in romstageRex-BC Chen
Initialize DRAM in romstage and configure to support fast calibration. Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54229 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-13soc/mediatek/mt8195: configure DMA buffer in DRAMRex-BC Chen
Set DRAM DMA to be non-cacheable to load blob correctly. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54052 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-13soc/mediatek/mt8195: Enable SCP SRAMRex-BC Chen
Enable SCP SRAM to allow module in SCPSYS to access DRAM. TEST=AFE acess DRAM successfully Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I40862f8d74e5aa17361f1c91ea31a10b0a4ffb31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54014 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-11soc/mediatek/mt8195: Enable and initialize eintYidi Lin
eint event mask register is used to mask eint wakeup source. All wakeup sources are masked by default. Since most MediaTek SoCs do not have this design, we can't modify the kernel eint upstream driver to solve the issue 'Can't wake using power button (cros_ec) or touchpad'. So we add a driver here to unmask all wakeup sources. Change-Id: I703d87e3dc49cf4e0b7ff0c75a6ea80245dd73d3 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54007 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-11soc/mediatek/mt8195: Disable UFS reference clockYidi Lin
UFS reference clock (refclk) is enabled by default, which will cause the UFSHCI to hold the SPM signal and lead to suspend failure. Since UFS kernel driver is not built-in, disable refclk in coreboot stage. Change UFSHCI base register to 0x11270000. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I1386e59f802a9e3c938a7e8dbeea547fbcb02709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-10soc/mediatek/mt8195: Add RTC driverYuchen Huang
Both mt8192 and mt8195 use MT659P RTC. Move mt8192/rtc.c to common folder and rename to rtc_mt6359p.c. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I73ea90512228a659657f2019249e7142c673e68e Reviewed-on: https://review.coreboot.org/c/coreboot/+/53897 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10soc/mediatek/mt8195: Add clk_buf driverYuchen Huang
Both mt8192 and mt8195 use mt6359p clk_buf. But mt8195 clk_buf uses legacy co-clock mode without srclken_rc. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Change-Id: Ie9ee91449a7a14e77231493f807b321b2dbaa6a6 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-10soc/mediatek/mt8195: Configure eMMC and SDCardWenbin Mei
Change-Id: I0ed82e860612e8a62f361e60d217280f775ab239 Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53895 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10soc/mediatek/mt8195: Add i2c driver supportkewei xu
TEST=write/read EEPROM on MT8195 EVB successfully Change-Id: Ia26e55512501e9758d7f5543d176730cf30ce03d Signed-off-by: kewei xu <kewei.xu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53894 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-07soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cacheYidi Lin
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52925 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05soc/mediatek/mt8195: Add mtcmos init supportWeiyi Lu
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: If7cd1f596f1406fa21d6586510e9956bb9846a6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-05soc/mediatek/mt8195: Add NOR-Flash supportRex-BC Chen
TEST=boot to romstage on MT8195 EVB Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I450281fb4b1750e59cb76f6b2083f0e2889fd4cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-05soc/mediatek/mt8195: Add SPI driver supportQii Wang
Add SPI controller driver code. Signed-off-by: Qii Wang <qii.wang@mediatek.com> Change-Id: I674763cdb0f338e123c121ede52278cfe96df091 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-05soc/mediatek/mt8195: add pmif/spmi/pmic driverRex-BC Chen
MT8195 also uses mt6359p so we can reuse most drivers. The only differences are IO configuaration, clock setting, and PMIC internal setting related to soc. Reference datasheet: MT6315 datasheet v1.4.2.pdf, RH-D-2019-0616. Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205. Change-Id: I73f9c9bf92837f262c15758f16dacf52261dd3a3 Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-28soc/mediatek/mt8195: Add PLL and clock init supportWeiyi Lu
Add PLL and clock init code. Add frequency meter and API for raising little CPU/CCI frequency. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I8ded0236d10826687f080bd5a213feb55d4bae03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52667 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/mediatek/mt8195: Add GPIO driverPo Xu
Signed-off-by: Po Xu <jg_poxu@mediatek.corp-partner.google.com> Change-Id: Ica1b1c80a851075599442298bb6675caf5c72f57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-26soc/mediatek/mt8195: Add timer supportYidi Lin
TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Asurada and Cherry P0 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ic6a87e7d5983bf14ad123de82ed670a22a7be1aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/52541 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/mediatek/mt8195: Initialize watchdogYidi Lin
MT8195 requires writing speical value to mode register to clear status register. This value is invalid on other platforms. We can do this safely in the common watchdog driver. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iba5b41f426fc38719bb343a220e0724bff229c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-13soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoCYidi Lin
TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 13:24:58 +0000