diff options
| author | Jitao Shi <jitao.shi@mediatek.com> | 2021-06-01 11:42:27 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-06-10 09:40:45 +0000 |
| commit | 435ee357e9c4e09032e4919b4b815fce1fc7d555 (patch) | |
| tree | daddaccf2d8cf67ce394775721eb2537306698d5 /src/soc/mediatek/mt8195/Makefile.inc | |
| parent | f1763ca7e501c0f02fa0fbc80d1d5fb69386ce64 (diff) | |
soc/mediatek/mt8195: add power and power control for eDP
1. Add API of TVD_PLL1 mt_pll_set_tvd_pll1_freq() for setting rate.
2. Add API of TVD_PLL1 edp_mux_set_sel() for mux sel.
3. Add eDP power domain control.
BUG=b:189985956
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: I9e43e0ffeb7b8bcd1786a8d2f5acbf22d5ab501f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55346
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8195/Makefile.inc')
| -rw-r--r-- | src/soc/mediatek/mt8195/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index e0536389c4..ae5bca046a 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -56,6 +56,7 @@ ramstage-y += ../common/mcu.c ramstage-y += ../common/mcupm.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c +ramstage-y += ../common/pll.c pll.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c ramstage-y += ../common/sspm.c |