soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC

TEST=boot from SPI-NOR and show console message at bootblock stage.

Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

1 files changed, 31 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
new file mode 100644
index 0000000000..ab7561f2d1
--- /dev/null
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -0,0 +1,31 @@
+ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y)
+
+bootblock-y += bootblock.c
+bootblock-y += ../common/mmu_operations.c
+bootblock-$(CONFIG_SPI_FLASH) += spi.c
+bootblock-y += ../common/timer.c
+bootblock-y += ../common/uart.c
+
+verstage-$(CONFIG_SPI_FLASH) += spi.c
+verstage-y += ../common/timer.c
+verstage-y += ../common/uart.c
+
+romstage-y += ../common/cbmem.c
+romstage-y += emi.c
+romstage-$(CONFIG_SPI_FLASH) += spi.c
+romstage-y += ../common/timer.c
+romstage-y += ../common/uart.c
+
+ramstage-y += emi.c
+ramstage-$(CONFIG_SPI_FLASH) += spi.c
+ramstage-y += soc.c
+ramstage-y += ../common/timer.c
+ramstage-y += ../common/uart.c
+
+CPPFLAGS_common += -Isrc/soc/mediatek/mt8195/include
+CPPFLAGS_common += -Isrc/soc/mediatek/common/include
+
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
+	./util/mtkheader/gen-bl-img.py mt8183 sf $< $@
+
+endif