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De-duplicate the MWAIT_RES define. Move it to intel/common/block.
Change-Id: I43903e4f02a549f53101e79f6febd42f2e54f98f
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49802
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It's only necessary to call get_option() with SLP_TYP S5.
Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49251
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I78ff11a56b38c4bc4f4f00115de1af4b73d4448c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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This change uses the newly added meminit block driver and updates ADL
SoC and mainboard code accordingly.
BUG=b:172978729
Change-Id: Ibcc4ee685cdd70eac99f12a5b5d79fdbaf2b3cf6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Change-Id: I3c1aa7f68eb03f04ddb9c1a5e960e3e2050a029c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49250
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Unify the debug messages on raised SMIs.
Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49248
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop the old, redundant code for mirroring LPC registers to DMI and make
use of the new common code.
Select the new Kconfig option for LPC DMI mirroring by the option
SOC_INTEL_COMMON_PCH_BASE, which is selected by platforms starting with
SPT, except APL and Xeon-SP. For Xeon-SP, select DMI and the new Kconfig
directly.
APL, even though it's younger than SPT, does not need mirroring.
Test: Set LGMR address by calling `lpc_open_mmio_window` and check that
both the PCI cfg and DMI LGMR register get written correctly.
Tested successfully on clevo/cml-u.
Change-Id: Ibd834f1474d986646bcebb754a17db97831a651f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Starting with SPT, LPC registers IOD, IOE, LGIR* and LGMR need to be
mirrored to their corresponding DMI registers. Add the required writes
to DMI registers, where the PCI config registers get written.
This is already done in soc code for IOD, IOE and LGIR* by mirroring
the registers later, during PCH init. Also the code mostly matches
accross the platforms. This common implementation will avoid delayed
mirroring of the registers and also deduplicate the code.
This change also adds a new Kconfig that will be selected by platforms
requiring mirroring of LPC IO/MMIO registers to their corresponding DMI
registers.
For making use of this common code, the redundant soc code needs to be
dropped and the newly introduced Kconfig option has to be selected. This
is done in the follow-up change.
Change-Id: I39f3bf4c486a1bbc112b2b453381de6da4bbac4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Commit 393992f (cpu/mp_init: Fix microcode lock) fixed the semantics
of parallel loading microcode updates.
So now '*parallel = 1' really means loading MCU in parallel, which
seems to fail inconsistently on around 10% of the APs.
Change-Id: I755dd302abbb58537d840852e8e290bea282a674
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49671
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change uses the newly added meminit block driver and updates TGL
SoC and mainboard code accordingly.
TEST=Verified that UPDs are configured correctly with and without this
change.
Change-Id: I6d58cd6568b7bbe03c4e3011b2301209893e85a9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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This change adds support for a common block memory driver that can be
used for performing the required operations to read SPD data for
different memory channel DIMMs. This data can then be used by the SoC
code to populate different memory related UPDs.
Most recent Intel platforms follow a similar pattern for configuring
FSP-M UPDs for initializing memory. These platforms use one of the
following topologies:
1. Memory down
2. DIMM modules
3. Mixed
Thus, SPD data is either obtained from CBFS (for memory down topology)
or from on-module EEPROM (for DIMM modules). This SPD data read from
CBFS or EEPROM is then passed into FSP-M using SPD UPDs for different
channels/DIMMs as per the memory organization.
Similarly, DQ/DQS configuration is accepted from mainboard and passed
into FSP-M using UPDs as per the FSP-M/MRC organization of memory
channels.
Different memory technologies on a platform support physical channels
of different widths. Since the data bus width is fixed for a platform,
the number of physical channels is determined by data bus width /
physical channel width. The number of physical channels are different
depending upon the size of physical channel supported by the memory
technology. FSP-M for a platform uses the same set of UPDs for
different memory technologies and aims at providing maximum
flexibility. Thus, the platform code needs to format mainboard inputs
for DQ, DQS and SPD into the UPDs appropriately as per the memory
technology used by the board.
Example: DDR4 on TGL supports 2 physical channels each 64-bit
wide. However, FSP-M UPDs assume channels 16-bit wide. Thus, FSP-M
provides 16 UPDs for SPDs (considering 2 DIMMs per channel and 8
channels with each channel 16-bit wide). Hence, for DDR4, only the SPD
UPDs for MRC channel 0 and 4 are supposed to be used.
This common driver allows the SoC to define the attributes of the
platform:
1. DIMMS_PER_CHANNEL: Maximum DIMMs that are supported per channel by
any memory technology on the platform
2. DATA_BUS_WIDTH: Width of the data bus.
3. MRC_CHANNEL_WIDTH: Width of the channel as used by the MRC to
define UPDs.
In addition to this, the SoC can define different attributes of each
memory technology supported by the platform using `struct
soc_mem_cfg`:
1. Number of physical channels
2. Physical channel to MRC channel mapping
3. Masks for memory down topologies
Using the above information about different memory technologies
supported by the platform and the mainboard configuration for SPD,
the common block memory driver reads SPD data and provides pointers to
this data for each dimm within each channel back to the SoC code. SoC
code can then use this information to configure FSP-M UPDs
accordingly. In addition to that, the common block driver also returns
information about how the channels are populated so that the SoC code
can use this information to expose DQ/DQS information in FSP-M UPDs.
This driver aims at minimizing the effort required for supporting
different memory technologies on any new Intel SoC by reducing per-SoC
effort to a table of configurations rather than having to implement
similar logic for each SoC.
BUG=b:172978729
Change-Id: I256747f0ffc49fb326cd8bc54a6a7b493af139c0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49040
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make IGD disable when mainboard user selects SOC_INTEL_DISABLE_IGD.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib297b339ce15ccb9212da32b27022610bc8aa2b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Creating named objects within a method is highly inefficient. So, pass a
reference to the OperationRegion field that needs to be updated instead.
Change-Id: I88272fc5cbe35427ccb5fc50789d47b66ace88fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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When SerialIO devices are disabled, their _STA method evaluates to 0,
which means the device is not present. It is expected that OSPM would
not attempt to change the power state of a device that is not present.
Lynxpoint does not have these checks, thus remove them from Broadwell.
Also remove the now-unused Arg1 parameter to avoid warnings from IASL.
Change-Id: Ic5e999ac1171ce49db66bec45c58d8aa5711ec53
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Id84a88933d32f60dd8d864d9a10d84a2b3c365ff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I06134e48b2d33c178883fc2047bcfbad417c6d02
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Ib0f425d74bc219ef518394526b51f2756eb95d61
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: Ic83a6a5db3b3d8a08c92064f8039d1bac825ffc3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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The xeon_sp/cpx has a second 'rc' heap inside FSP-M that is statically
allocated at the start of CAR. This breaks FSP 2.0 specification. This
can be worked around in the linker scripts to make sure coreboot and
FSP-M don't fight over the same memory.
Tested
- on ocp/deltalake: boot and the "Smashed stack detected in
romstage!" message at the end of romstage is gone.
- qemu/i440fx: BUILD_TIMELESS=1 results in the same binary.
Change-Id: I6d02b8a46a2a8ef00f34d8f257595d43f5d3d590
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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Change-Id: I7cf5f97c3229fe6a72d70a36e8cff49ff3cf611b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The ids used in function `soc_get_pch_series()` are not valid for
Icelake. Since it's not even used, instead of fixing it, drop it.
Change-Id: I4a1ee4b84f11ea314cb666ce4506ff90168da0ca
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49875
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We already know the PCH type at build time, so there is no need to do
runtime detection. Thus, use Kconfig and drop `get_pch_series()`.
Change-Id: I470871af5f5954e91a8135fddf4a2297a514d740
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49874
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename and split functions to match what Haswell does.
Change-Id: I4f3e997dd934bdf7717a70603d9413eae93cf181
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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It is no longer necessary.
Change-Id: Ib37c9de83badc6339dca6916aec8c34a43797652
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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All Broadwell boards only use the `mainboard_pre_raminit` function to
call `mainboard_fill_pei_data` and optionally `mainboard_fill_spd_data`.
Move the declaration and weak definition of `mainboard_fill_spd_data` to
platform code, replace the call to `mainboard_pre_raminit` in romstage.c
with calls to `mainboard_fill_pei_data` and `mainboard_fill_spd_data`,
and delete all other instances of `mainboard_pre_raminit` for Broadwell.
Finally, delete now-empty romstage.c and spd.h files from mainboards.
Change-Id: I3334b20bd7138bb753b996a137ff106e87c6e8a5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Make it optional and change its signature.
Change-Id: I4b5f3fb08e8954514ebf39e72c95aa62d66856d7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Broadwell boards now use the CPU code for Haswell. Therefore, these
devicetree options are no longer used anywhere and can be removed.
Change-Id: Ib0d1b6eecc11a70d1a2614669353a8040c860535
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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This allows us to drop many now-redundant Kconfig options.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
The default configuration file also remains identical, as expected.
Change-Id: I20b0200550508679bf2533342ce918b221dcf81e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Broadwell no longer has CPU code.
Change-Id: I9c9717439a702dddaa613a30e6f3da29887ec4bd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46951
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All boards now use Haswell's CPU code, which also supports Broadwell.
Change-Id: Ia0b8f7bf64334dd965baad0a30a7bb0ed81c4cac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46950
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that the boards use Haswell's CPU code, Broadwell can be updated.
Change-Id: If07e5272f07edb59bb18eef1f80d7d5807b26e66
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46949
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This allows individual boards to be adapted to use Haswell CPU code.
Also rename the CPU_SPECIFIC_OPTIONS symbol to avoid any collisions.
Change-Id: I65e878dacf0a0d53fd8d4defce6684f4ceb92588
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46944
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This allows the correct Haswell and Lynxpoint code to be used.
Change-Id: Icbfc5bb11b1ea755a143fa340a3971376f4e5e91
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46958
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I01be1b9dfefcfcf037de4153e9540c7258dc160f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49818
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create uniform logging for the (unlikely) case of a CBMEM
entry disappearing.
Change-Id: I7c5414a03d869423c8ae5192a990fde5f9582f2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I37781c1423b49130ffd0d5f9fbdd28a36c9c6179
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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It is never allowed for ELOG to modify the state.
Change-Id: Ie24df3969a3744f27b23997471666e2490e24b84
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add microcode from 3rdparty repo for:
- 06-a5-02 (CPUID signature: 0xa0652)
Change-Id: I95419f44a1e804ce31338fe6d863f156c655321b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47915
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop LPC pad configuration code since all boards now do pad
configuration on their own. The comment about LPC_CLKRUNB when using
eSPI is moved to `Documentation/getting_started/gpio.md`.
Change-Id: I710d6aee8c3b2c8282cd321cd0688b9b26abea07
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49410
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Add SOC_INTEL_ALDERLAKE_PCH_M option in Kconfig
2. Select number of I/O based on PCH
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I38783595e4b85abf5b3bec234ba01667bd9ba754
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49630
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Alder Lake M specific CPU, System AGent, PCH (Alder Point aka
ADP),
IGD device IDs.
Document Number: 619501, 626817
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: Ib13fe229f9e65eae8967aa20e28e29ac5c319265
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49629
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I5c277a4b8536fd79bda040d4ada9b0c454399b09
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49356
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For the time being every soc/intel selects ACPI_SOC_NVS
and pwrs is a required field for the common initialisation
implementation of followup work.
Change-Id: I4a0c7eb35f0646898e49fad15c6448607c398731
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49493
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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0 is converted to not used, so use a special value to allow using PCIe
root port #1.
Change-Id: I2d64afc9bb4627913492edad8f36566e7fb18166
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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This change updates pcie_rp.h to reflow the comment blocks to fit
within 80 columns to match the original style of the file. This
addresses comment received on
CB:49370 (https://review.coreboot.org/c/coreboot/+/49370/comment/0f3fe10d_4e218b5f/).
Change-Id: I565ad602e0e3a2ee09e8345479d82e2ce0a31fd0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Make IGD disable when mainboard user selects SOC_INTEL_DISABLE_IGD.
TEST=Able to get depthcharge pre-OS splash screen with AMD Radeon RX
5700 PCI-E DGPU when mainboard user selects SOC_INTEL_DISABLE_IGD.
Change-Id: Ibbe9c8c4d77018de83815d7d203284b1fbc0da58
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This SOC_INTEL_DISABLE_IGD Kconfig will allow to skip IGD
initialization using FSP GOP and eventually disable the IGD.
TEST=Able to get depthcharge pre-OS splash screen when mainboard
user selects SOC_INTEL_DISABLE_IGD with below HW/FW/SW
configuration:
HW: ADLRVP + AMD Radeon RX 5700 PCI-E DGPU
FW: coreboot with depthcharge as payload for ADLRVP and OpRom for
AMD PCI-E DGPU
SW: Chrome OS RC10 release
Change-Id: I465541cb45c9022d53a5beb3fff1f80660c357c9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I28be6091097f713472d5ca3b8b0921ee71238cf0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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The code for setting the LPC generic memory range uses an array of fixed
address ranges not needing explicit decoding, to decide if the address
needs to be written to the LGMR register. Most platforms only mistakenly
add the PCH reserved mmio range, that is not decoded generally,
effectively breaking the mechanism. Only APL uses the array correctly.
That code, in it's current state, does not work (except for APL) and
currently, there is not a single user. Thus, drop it before people start
using it.
Change-Id: I723415fedd1b1d95c502badf7b0510a1338b11ac
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Only amd/picasso and amd/stoneyridge have reference to
PCNT and that could be replaced with acpigen.
Remove the PCNT name from GNVS OperationRegion elsewhere.
Change-Id: I7dd45a840b3585fd24c31fd923b991c34ab4d783
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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- Return the busno based on the stack number.
- Replace pci_mmio_read_config32 with pci_io_read_config32 to get the
register value before mapping the MMIOCFG space.
- Remove the plural `s` as the function now provides one bus number.
Change-Id: I6e78e31b8ab89b1bdcfdeffae2e193e698385186
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The layout of GNVS has expectation for a fixed size
array for chromeos_acpi_t. This allows us to reduce
the exposure of <chromeos/gnvs.h>.
If chromeos_acpi_t was the last entry in struct global_nvs
padding at the end is also removed.
If device_nvs_t exists, place a properly sized reserve for
chromeos_acpi_t in the middle.
Allocation from cbmem is adjusted such that it matches exactly
the OperationRegion size defined inside the ASL.
Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I96b302f5a1f10daaed017a2453d1568a2e49e4ad
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I2ac1035585b32ba65d0725067cff0c12c9f748c1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Icf4247a0a5fb7950c69c8f229a6629a4fa6980f7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I3aec07d782e4315120a4365a65bdbcbf4a22e6f2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
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Change-Id: I646583f7f0d0e0f6a91bc99b7edda964337d837e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
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Change-Id: Icc4954bcc1540f1935b0e34107febb4a1e947a36
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
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Change-Id: Id5bf9255e9a16a4f311e3b15eb77ad6e4bb13f66
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
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According ADL EDS to update the PCH and CPU PCIe RP table.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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L1_substates_control is common define. Move out of soc level.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I54574b606985e82d00beb1a61cce3097580366a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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In case of CPU PCIe RPs, the RP numbers might not be contiguous for
all the functions in a slot.
Example: In ADL, RP1 is 00:06.0, RP2 is 00:01.0 and RP3 is 00:06.2 as
per the FSP expectations.
Hence, this change updates the defintion of `struct pcie_rp_group` to
include a `start` member which indicates the starting PCI function
number within the group. All common functions for PCIe RP are
accordingly updated to take the `start` member into account.
Thus, in the above example, ADL can provide a cpu_rp_table as follows:
{
{ .slot = PCIE_SLOT_6, .start = 0, .count = 1 },
{ .slot = PCIE_SLOT_1, .start = 0, .count = 1 },
{ .slot = PCIE_SLOT_6, .start = 2, .count = 1 },
}
Since start defaults to 0 when uninitialized, current PCH RP group
tables don't need to be updated.
Change-Id: Idf80a0f29e7c315105f76a7460c8e1e8f9a10d25
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49370
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Exit early if the chipset power state info isn't in CBMEM. Return -1 in
order to ensure the one caller of this function exits early as well.
Found-by: Coverity CID 1442304
Change-Id: Ifa42ba3024d3144de486d90ed7752820482549bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49359
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change affects Intel CPUs only. As most platforms are doing
uCode update using FIT, they aren't affected by this code either.
Update microcode in MP-init using a single spinlock when running on
a Hyper-Threading enabled CPU on pre FIT platforms.
This will slow down the MP-init boot flow.
Intel SDM and various BWGs specify to use a semaphore to update
microcode on one thread per core on Hyper-Threading enabled CPUs.
Due to this complex code would be necessary to determine the core #ID,
initializing and picking the right semaphore out of CONFIG_MAX_CPUS / 2.
Instead use the existing global spinlock already present in MPinit code.
Assuming that only pre-FIT platforms with Hyper-Threading enabled and at
most 8 threads will ever run into this condition, the boot delay is
negligible.
This change is a counterproposal to the previous published patch series
being much more unsophisticated.
Change-Id: I27bf5177859c12e92d6ce7a2966c965d7262b472
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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As a requirement of TCSS this setting needs to be correctly set
to determine what Type-C ports are enabled on the platform. Without
this value correctly set there can be adverse effects on the other
TCSS specific values.
BUG=b:159151238
BRANCH=firmware-volteer-13672.B
TEST=Built image for Voxel and verified that S0ix cycles no longer
fail when the IomPortPad is set to 0
Change-Id: I6c5260cda71041439fe89d15bd3cafd4052ef1e7
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Target added to INTERMEDIATE all operate on coreboot.pre, each modifying
the file in some way. When running them in parallel, coreboot.pre can be
read from and written to in parallel which can corrupt the result.
Add a function to create those rules that also adds existing
INTERMEDIATE targets to enforce an order (as established by evaluation
order of Makefile.inc files).
While at it, also add the addition to the PHONY target so we don't
forget it.
BUG=chromium:1154313, b:174585424
TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2
timeout and sercon) and saw that they were executed.
Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I61a9b07ec3fdaeef0622df82e106405f01e89a9e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48719
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I515e830808a95eee3ce72b16fd26da6ec79dac85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48718
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change lets IOM consider all USB connected devices as device
attached(DA) scenario. While connecting a typec-to-a dongle, IOM would
disable TC cold and help to resolve enemuration failure after usb3
device is plugged into the dongle.
BUG=b:173054070
TEST=Build and boot on delbin.
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49244
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The name `..._index` is confusing since the maximum index of an array is
not `ARRAY_SIZE(array)` but `ARRAY_SIZE(array) - 1`.
Rename `uart_max_index` to `uart_ctrlr_config_size` to make the name
match the variable´s value.
Change-Id: I7409c9dc040c3c6ad718abc96f268c187d50d79c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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It is only used in one place, and there's two other equivalent macros.
Change-Id: I7c8241e28f688abd2df8180559dd02ee441c7023
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This change adds a helper function `pcie_rp_enable_mask()` that
returns a 32-bit mask indicating the status (enabled/disabled) of PCIe
root ports (in the groups table) as configured by the mainboard in the
device tree.
With this helper function, SoC chip config does not need to add
another `PcieRpEnable[]` config to identify what root ports are
enabled.
Change-Id: I7ce5fca1c662064fd21f0961dac13cda1fa2ca44
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48968
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=Able to build and boot ADLRVP.
Change-Id: Ia331998b46abcf10e939078dea992589f09139bd
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49301
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add SLP_S0 residency register and enable LPIT support.
Change-Id: Id1abbe8dcb7796eeb26ccb72f1f26cf7a040dba4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49048
Reviewed-by: Lance Zhao
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1
boots without crashing with an INTERNAL_POWER_ERROR.
Change-Id: Icccd9d15a9e9a22c9bfe7a9843e95d77013c9c8f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49047
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1
boots without crashing with an INTERNAL_POWER_ERROR.
- Windows and Linux tested on google/akemi
- Linux tested on clevo/cml-u
Change-Id: I51fdf52419aa7f059b70a906fd8bdac88d5b6046
Tested-By: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49046
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for the Intel LPIT table to support reading Low Power Idle
Residency counters by the OS. On platforms supporting S0ix sleep states
there can be two types of residencies:
* CPU package PC10 residency counter (read from MSR via FFH interface)
* PCH SLP_S0 assertion residency counter (read via memory mapped
interface)
With presence of one or both of these counters in the LPIT table, Linux
dynamically adds the corresponding attributes to the cpuidle sysfs
interface, that can be used to read the residency timers:
* /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
* /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us
The code in src/acpi implements generic LPIT support. Each SoC or
platform has to implement `acpi_fill_lpit` to fill the table with
platform-specific LPI state entries. This is done in this change for
soc/intel/common, while being added as its own compilation unit, so SoCs
not yet using common acpi code (like Skylake) can use it, too.
Reference:
https://uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.pdf
Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1
boots without crashing with an INTERNAL_POWER_ERROR.
- Windows and Linux tested on google/akemi together with CB:49046
- Linux tested on clevo/cml-u, supermicro/x11ssmf together with CB:49046
Change-Id: I816888e8788e2f04c89f20d6ea1654d2f35cf18e
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Drop the support for the Intel Cannon Lake SoC for various reasons:
* Most people can't use coreboot on Cannon Lake, since the required FSP
binaries aren't publicly available. Given that FSP binaries for several
newer platforms have been released, it's very unlikely that Cannon Lake
FSP will ever be released.
* It seems there is no interest in this, since the reference mainboard
is the only available mainboard in tree.
Also, remove the related reference mainboard intel/cannonlake_rvp and
its FSP headers in intel/fsp2_0/cannonlake.
Change-Id: I8f698e16099acb45444b2bc675642d161ff8c237
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48775
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates various uart_* functions to use simple(_s_)
variants of PCI functions. This is done for a few reasons:
* __SIMPLE_DEVICE__ check can be dropped since the same data type can
be used in early stages and ramstage.
* Removes the requirement on early stage to walk the device tree to
get access to the device structure. This allows linker-based device
tree optimizations for early stages.
As part of this change, uart_get_device() is refactored and a new
function uart_console_get_devfn() is added which returns pci_devfn_t
in MMCONF format. It is then used directly by the _s_ variants of PCI
functions.
Change-Id: I344037828118572ae5eb27c82c496d5e7a508a53
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This change renames `struct uart_gpio_pad_config` to `struct
uart_controller_config` and adds a new parameter devfn (which expects
devfn for the UART controller corresponding to the index in
PCI_DEVFN() format). This gets rid of the SoC callback to get `struct
device` pointer to the UART controller device.
Change-Id: Id0712a0038f2cc1a61b8b5a58fa155f14e7949a5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49212
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Prevent the FSP from writing its default SVID SDID values of 8086:7270
for internal devices as this locks most of the registers. Allows the
subsystemid values set in devicetree to be used.
A description of this SSID table override behavior, along with example
code, is provided in the TigerLake FSP Integration Guide, section
15.178 ("SI_CONFIG Struct Reference").
The xHCI and HDA devices have RW/L registers rather than RW/O registers.
They can be written to multiple times but cannot be modified after
being locked, which happens during FspSiliconInit. Because coreboot
populates subsystem IDs after SiliconInit, these devices specifically
must be written beforehand or will otherwise be locked with their
default values of 0:0.
Tested by checking lspci output on System76 galp3-c (WHL), oryp5 (CFL),
and oryp6 (CML).
References:
- TigerLake FSP Integration Guide
- Intel Document Number 337868-002
Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49104
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The xHCI controller supports waking the system from S1-S4.
Thus specify that the deepest sleep state is S4 in _PRW.
Tested on Prodrive/hermes. The board now wakes from S4 as well by
pressing a key on the USB keyboard.
Change-Id: I0bb266e70ee6b4eb8922671b7d0078db0d29a1da
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49224
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. Create new Kconfig MAX_CPU_ROOT_PORTS and MAX_PCH_ROOT_PORTS as per
EDS.
2. Add new chip variable to enable/disable CPU PCIE RPs from mainboards.
3. Rename PcieRpEnable to PchPcieRpEnable.
4. Enable CPU RPs as below in mainboard devicetree.cb
RP1: PEG60 : 0:6:0 : CPU SSD1
RP2: PEG10 : 0:1:0 : x8 CPU Slot
RP3: PEG62 : 0:6:2 : CPU SSD2
Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49136
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is needed to allow switching to Haswell CPU code in the future.
Change-Id: Ic642f32f9c4a269a66ac470b7a7217f20ff8bfba
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46886
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Only a google/cyan variant evalutes BDID in ASL.
Change-Id: I3d839333333b4762ae5350734c85471a3c12838a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49003
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic779a668ebaa4f0c9bdef95fd6de8f0179e8a534
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49004
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace acpi_create_gnvs() under soc/ to reflect their
changed funcionality.
Change-Id: I7bdbe0d6f795252e713e9785ada2b6320e6604b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48717
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename these to soc_fill_gnvs() and move the callsite away
from mb/.
Change-Id: I760c36f65c6122103f2be98fc11ee13832c2772e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48716
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename acpi_create_gnvs() functions under mb/ to reflect
their changed functionality.
Remove now empty mb/acpi_tables.c files.
Change-Id: Ia366867ef73d1ade9805dc29b8e14b3073f44f60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48707
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Name the common part of GNVS initialisation as soc_fill_gnvs().
It is also moved before the call to acpi_create_gnvs(), which
followup will rename to mainbord_fill_gnvs() to reflect that
implementation is under mb/.
Change-Id: Ic4cf1548b65a86212d6e45d460fcd23bb8036365
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48706
Reviewed-by: Lance Zhao
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I45a2d9cb7f07609a1ff03fd70f17c3f2d4f013b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48705
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move GNVS details to different function, called
from acpi_create_gnvs().
Change-Id: Ief02c078fe37753c0d29418394a351105a1aacc8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48704
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Already done in common gnvs_get_or_create() implementation
once gnvs_chromeos_ptr() is defined for platforms.
Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Already done from common gnvs_get_or_create() implementation
after gnvs_cbmc_ptr() is defined.
Change-Id: I77c292cd9590d7fc54d8b21ea62717a2d77e5ba4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48702
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allocation now happens prior to device enumeration. The
step cbmem_add() is a no-op here, if reached for some
boards. The memset() here is also redundant and becomes
harmful with followup works, as it would wipe out the
CBMEM console and ChromeOS related fields without them
being set again.
Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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uart_common_init is not used outside of
soc/intel/common/block/uart.c. This change restricts the scope to this
file and drops the declaration from uart.h
Change-Id: I499a53506f9b2e91ecc7334bf9b023d342e802fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49211
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates the parameter passed into `lpss_set_power_state()`
from struct device * to pci_devfn_t. This allows the users in the
early stages to use pci_devfn_t instead of having to walk the device
tree to get a pointer to the relevant device structure. It is
important for optimizing out unnecessary components of the device tree
from the early stages.
Change-Id: Ic9e32794da65348fe2a0a2791db47ab83b64cb0f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49210
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change drops the parameter `struct device *dev` from the function
`soc_get_gen_io_dec_range()`. This function uses the parameter dev to
get a pointer to config structure for extracting the decode ranges
configured by mainboard in device tree. However, there is no separate
chip driver for the LPC device which means that the SoC code can use
`config_of_soc()` to get to SoC chip config instead of using the LPC
device.
This change is being done in preparation to clean up the device
tree/chip config access in early stages that allows for optimizing
the inclusion of device tree elements in the early stages.
Change-Id: I3ea53ddc771f592dd0ea5e5e809be2d2eff7f16d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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USB3 is in CPU and USB2 in PCH on Tigerlake. Cross die messaging is
implemented between CPU and PCH through the IOSF SB bridge. a PCH xHCI
USB2 port reset event issued by the xHCI driver shall trigger a message
upstream to CPU to wake it from the low power state which allows a USB3
device that downgraded to USB2 to upgrade back to USB3.
BUG=b:176575892
TEST=Built and booted to kernel on Voxel board.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I672f30a117980bc10bd71e9b77c5fa76286b9f5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49052
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I125e40204f3a9602ee5810d341ef40f9f50d045b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48897
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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