soc/intel/alderlake: Update PCH and CPU PCIe RP table

According ADL EDS to update the PCH and CPU PCIe RP table.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

5 files changed, 55 insertions, 9 deletions

diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc
index d962b75079..f31cf98dd7 100644
--- a/src/soc/intel/alderlake/Makefile.inc
+++ b/src/soc/intel/alderlake/Makefile.inc
@@ -25,6 +25,7 @@ bootblock-y += p2sb.c
 romstage-y += espi.c
 romstage-y += gpio.c
 romstage-y += meminit.c
+romstage-y += pcie_rp.c
 romstage-y += reset.c
 
 ramstage-y += acpi.c
@@ -38,6 +39,7 @@ ramstage-y += gpio.c
 ramstage-y += lockdown.c
 ramstage-y += me.c
 ramstage-y += p2sb.c
+ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
 ramstage-y += smmrelocate.c
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index 95b6b8f307..c7e3fb8c2f 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -14,15 +14,10 @@
 #include <soc/intel/common/vbt.h>
 #include <soc/itss.h>
 #include <soc/pci_devs.h>
+#include <soc/pcie.h>
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>
 
-static const struct pcie_rp_group pch_lp_rp_groups[] = {
-	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8 },
-	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 4 },
-	{ 0 }
-};
-
 #if CONFIG(HAVE_ACPI_TABLES)
 const char *soc_acpi_name(const struct device *dev)
 {
@@ -150,7 +145,7 @@ void soc_init_pre_device(void *chip_info)
 	soc_fill_gpio_pm_configuration();
 
 	/* Swap enabled PCI ports in device tree if needed. */
-	pcie_rp_update_devicetree(pch_lp_rp_groups);
+	pcie_rp_update_devicetree(get_pch_pcie_rp_table());
 }
 
 static struct device_operations pci_domain_ops = {
diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h
index d86e81ddc2..098c31daa5 100644
--- a/src/soc/intel/alderlake/include/soc/pci_devs.h
+++ b/src/soc/intel/alderlake/include/soc/pci_devs.h
@@ -22,6 +22,9 @@
 #define  SA_DEV_ROOT		PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
 #endif
 
+#define SA_DEV_SLOT_CPU_1	0x01
+#define  SA_DEVFN_CPU_PCIE1_0	PCI_DEVFN(PCH_DEV_SLOT_CPU_1, 0)
+
 #define SA_DEV_SLOT_IGD		0x02
 #define  SA_DEVFN_IGD		PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
 #define  SA_DEV_IGD		PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
@@ -34,8 +37,9 @@
 #define  SA_DEVFN_IPU		PCI_DEVFN(SA_DEV_SLOT_IPU, 0)
 #define  SA_DEV_IPU		PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
 
-#define SA_DEV_SLOT_CPU_PCIE	0x06
-#define  SA_DEVFN_CPU_PCIE	PCI_DEVFN(SA_DEV_SLOT_CPU_PCIE, 0)
+#define SA_DEV_SLOT_CPU_6	0x06
+#define  SA_DEVFN_CPU_PCIE6_0	PCI_DEVFN(PCH_DEV_SLOT_CPU_6, 0)
+#define  SA_DEVFN_CPU_PCIE6_2	PCI_DEVFN(PCH_DEV_SLOT_CPU_6, 2)
 
 #define SA_DEV_SLOT_TBT		0x07
 #define SA_DEVFN_TBT(x)		PCI_DEVFN(SA_DEV_SLOT_TBT, (x))
diff --git a/src/soc/intel/alderlake/include/soc/pcie.h b/src/soc/intel/alderlake/include/soc/pcie.h
new file mode 100644
index 0000000000..cd76d09e4a
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/pcie.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_ALDERLAKE_PCIE_H__
+#define __SOC_ALDERLAKE_PCIE_H__
+
+#include <intelblocks/pcie_rp.h>
+
+const struct pcie_rp_group *get_pch_pcie_rp_table(void);
+const struct pcie_rp_group *get_cpu_pcie_rp_table(void);
+
+#endif /* __SOC_ALDERLAKE_PCIE_H__ */
diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c
new file mode 100644
index 0000000000..4ec24c265c
--- /dev/null
+++ b/src/soc/intel/alderlake/pcie_rp.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/pcie_rp.h>
+#include <soc/pci_devs.h>
+#include <soc/pcie.h>
+
+static const struct pcie_rp_group pch_lp_rp_groups[] = {
+	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8 },
+	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 4 },
+	{ 0 }
+};
+
+const struct pcie_rp_group *get_pch_pcie_rp_table(void)
+{
+	return pch_lp_rp_groups;
+}
+
+/*
+ * ADL-P FSP define CPU RP as below:
+ * RP1: PEG60 : 0:6:0 : x4 CPU Slot
+ * RP2: PEG10 : 0:1:0 : x8 CPU Slot
+ * RP3: PEG62 : 0:6:2 : x4 CPU Slot
+ */
+static const struct pcie_rp_group cpu_rp_groups[] = {
+	{ .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1 },
+	{ .slot = SA_DEV_SLOT_CPU_1, .start = 0, .count = 1 },
+	{ .slot = SA_DEV_SLOT_CPU_6, .start = 2, .count = 1 },
+	{ 0 }
+};
+
+const struct pcie_rp_group *get_cpu_pcie_rp_table(void)
+{
+	return cpu_rp_groups;
+}