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authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-12-19 16:19:44 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-18 18:02:27 +0000
commit66c6413c69abb7335efc4ea07f4c811c042704b6 (patch)
tree06d58b85da4c779cca7b78e33a069ea03a4e69e4 /src/soc/intel
parentc4a6628a6fe4f5400b7abe1478d0b0b21cb8200f (diff)
ACPI: Refactor ChromeOS specific ACPI GNVS
The layout of GNVS has expectation for a fixed size array for chromeos_acpi_t. This allows us to reduce the exposure of <chromeos/gnvs.h>. If chromeos_acpi_t was the last entry in struct global_nvs padding at the end is also removed. If device_nvs_t exists, place a properly sized reserve for chromeos_acpi_t in the middle. Allocation from cbmem is adjusted such that it matches exactly the OperationRegion size defined inside the ASL. Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/include/soc/nvs.h8
-rw-r--r--src/soc/intel/baytrail/include/soc/nvs.h6
-rw-r--r--src/soc/intel/braswell/include/soc/nvs.h6
-rw-r--r--src/soc/intel/broadwell/include/soc/nvs.h6
-rw-r--r--src/soc/intel/common/block/include/intelblocks/nvs.h8
-rw-r--r--src/soc/intel/skylake/include/soc/nvs.h8
6 files changed, 3 insertions, 39 deletions
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index ab7021cf1a..ae1ae42e1d 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -10,8 +10,6 @@
#define _SOC_APOLLOLAKE_NVS_H_
#include <stdint.h>
-#include <commonlib/helpers.h>
-#include <vendorcode/google/chromeos/gnvs.h>
struct __packed global_nvs {
/* Miscellaneous */
@@ -35,12 +33,6 @@ struct __packed global_nvs {
uint64_t elng; /* 0x35 - 0x3C EPC Length */
uint64_t a4gb; /* 0x3D - 0x44 Base of above 4GB MMIO Resource */
uint64_t a4gs; /* 0x45 - 0x4C Length of above 4GB MMIO Resource */
- uint8_t unused[179];
-
- /* ChromeOS specific (0x100 - 0xfff) */
- chromeos_acpi_t chromeos;
};
-check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-
#endif /* _SOC_APOLLOLAKE_NVS_H_ */
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index 6eaf2c804c..1640886d6c 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -4,8 +4,6 @@
#define _BAYTRAIL_NVS_H_
#include <stdint.h>
-#include <commonlib/helpers.h>
-#include <vendorcode/google/chromeos/gnvs.h>
#include <soc/device_nvs.h>
struct __packed global_nvs {
@@ -50,12 +48,10 @@ struct __packed global_nvs {
u8 unused[76];
/* ChromeOS specific (0x100-0xfff) */
- chromeos_acpi_t chromeos;
+ u8 chromeos_reserve[0xf00];
/* Baytrail LPSS (0x1000) */
device_nvs_t dev;
};
-check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-
#endif /* _BAYTRAIL_NVS_H_ */
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 2184245aa8..2ea114b00c 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -4,9 +4,7 @@
#define _SOC_NVS_H_
#include <stdint.h>
-#include <commonlib/helpers.h>
#include <soc/device_nvs.h>
-#include <vendorcode/google/chromeos/gnvs.h>
struct __packed global_nvs {
/* Miscellaneous */
@@ -52,12 +50,10 @@ struct __packed global_nvs {
u8 unused[76];
/* ChromeOS specific (0x100-0xfff) */
- chromeos_acpi_t chromeos;
+ u8 chromeos_reserve[0xf00];
/* LPSS (0x1000) */
device_nvs_t dev;
};
-check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-
#endif /* _SOC_NVS_H_ */
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 2fe7bc8b70..e0e805253a 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -4,9 +4,7 @@
#define _BROADWELL_NVS_H_
#include <stdint.h>
-#include <commonlib/helpers.h>
#include <soc/device_nvs.h>
-#include <vendorcode/google/chromeos/gnvs.h>
struct __packed global_nvs {
/* Miscellaneous */
@@ -42,12 +40,10 @@ struct __packed global_nvs {
u8 unused2[76];
/* ChromeOS specific (0x100 - 0xfff) */
- chromeos_acpi_t chromeos;
+ u8 chromeos_reserve[0xf00];
/* Device specific (0x1000) */
device_nvs_t dev;
};
-check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-
#endif
diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h
index 38edfc769c..2f3ac1cc0b 100644
--- a/src/soc/intel/common/block/include/intelblocks/nvs.h
+++ b/src/soc/intel/common/block/include/intelblocks/nvs.h
@@ -4,8 +4,6 @@
#define SOC_INTEL_COMMON_BLOCK_NVS_H
#include <stdint.h>
-#include <commonlib/helpers.h>
-#include <vendorcode/google/chromeos/gnvs.h>
struct __packed global_nvs {
/* Miscellaneous */
@@ -28,12 +26,6 @@ struct __packed global_nvs {
u8 uior; /* 0x2f - UART debug controller init on S3 resume */
u64 a4gb; /* 0x30 - 0x37 Base of above 4GB MMIO Resource */
u64 a4gs; /* 0x38 - 0x3f Length of above 4GB MMIO Resource */
- u8 unused[192];
-
- /* ChromeOS specific (0x100 - 0xfff) */
- chromeos_acpi_t chromeos;
};
-check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-
#endif
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 303427653c..3d48d4d486 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -4,8 +4,6 @@
#define _SOC_NVS_H_
#include <stdint.h>
-#include <commonlib/helpers.h>
-#include <vendorcode/google/chromeos/gnvs.h>
struct __packed global_nvs {
/* Miscellaneous */
@@ -48,12 +46,6 @@ struct __packed global_nvs {
u64 elng; /* 0x4C - 0x53 EPC Length */
u64 a4gb; /* 0x54 - 0x5B Base of above 4GB MMIO Resource */
u64 a4gs; /* 0x5C - 0x63 Length of above 4GB MMIO Resource */
- u8 rsvd[156];
-
- /* ChromeOS specific (0x100 - 0xfff) */
- chromeos_acpi_t chromeos;
};
-check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-
#endif