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2022-09-27acpi/acpi_pm.c: refactor acpi_pm_state_for_* functionsFabio Aiuto
Use just one function to get the chipset powerstate and add an argument to specify the powerstate claimer {RTC,ELOG,WAKE} and adjust the failure log accordingly. TEST: compile tested and qemu emulation successfully run Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I8addc0b05f9e360afc52091c4bb731341d7213cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/67618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-22soc/intel/spi: Move BIOS flash SPI controllers to fast SPI driverWerner Zeh
There are two classes of SPI controllers on Intel chipsets: * generic usable SPI controllers * SPI controller hosting the BIOS flash (fast SPI controller) While the first class can be used for generic peripheral attachment the second class mostly controls the BIOS flash and a TPM device (if enabled). The generic SPI driver is not fully applicable to the fast SPI controller. In addition, the fast SPI controller reports the reserved MMIO range used for the BIOS flash mapping so that the OS is aware of this range. This patch moves the fast SPI controller of all known SoCs to the fast SPI driver in common code. In addition, the PCI device for the fast SPI controller is removed from the function 'spi_soc_devfn_to_bus' as this is a callback of the generic SPI driver. Change-Id: Ia881c1d274acdcf7f042dd8284048a7dd018a84b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-20soc/intel/alderlake: Explicitly disable Energy Efficiency TurboJeremy Compostella
FSP silicon 3347 changed the default value of the EnergyEfficientTurbo Updateable Product Data (UPD), enabling the Energy Efficient Turbo feature by default. This feature prevents the cores from entering Turbo frequency under heavy load. As a result of this FSP change, coreboot explicitly disables this feature to stay consistent with commit `caa5f59279e Revert "soc/intel/alderlake: Enable energy efficiency turbo mode"'. BRANCH=firmware-brya-14505.B BUG=b:246831841 TEST=verify that bit 19 of MSR 0x1fc is set. 'iotools rdmsr 0 0x1fc' Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I7498f87eb4be666b34cfccd0449a2b67a92eb9db Reviewed-on: https://review.coreboot.org/c/coreboot/+/67650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-09-20soc/intel/alderlake: Add power state thresholdsGaggery Tsai
This patch adds power state 1/2/3 threshold setting interfaces and pass the settings to FSP. BUG=b:229803757 BRANCH=None TEST=Add psi1threshold and psi2threshold to overridetree.cb and enable FSP log to ensure the settings are incorrect. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: I0330ede4394ebc2d3d32e4b78297c3cb328660d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-09-16soc/intel/alderlake: Set FSP-S GnaEnable based on devicetreeJeremy Soller
Change-Id: Ifd25416c55c4dba1709f74cdedc0c58e881d6266 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-12soc/intel/adl: Disable D3cold when legacy S3 is enabledLean Sheng Tan
D3Cold isn't supported in S3. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I072f47737ef38c44b6a676019e9a73868ff17e5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67413 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08soc/intel/alderlake: add power limits for Alder Lake-N 7W socSimon Yang
Missing power limit setting for Alder-Lake-N 7W soc. Document reference: 645548 and 646929 BUG=b:245440443 BRANCH=None TEST=Build FW and test on nivviks board and there is no error message "unknown SA ID: 0x4617, skipped power limits configuration." Signed-off-by: Simon Yang <simon1.yang@intel.com> Change-Id: Iefe17f5b574cc319fe9aad3850401a8aa8e31270 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-09-05soc/intel/alderlake: Remove dependency of FSP-S CpuMpPei ModuleSubrata Banik
This patch fixes a hidden issue present inside FSP-S while coreboot decides to skip performing MP initialization by overriding FSP-S UPDs as below: 1. CpuMpPpi ------> Passing `NULL` as coreboot assume FSP don't need to use coreboot wrapper for performing any operation over APs. 2. SkipMpInit -----> Set `1` to let FSP know that coreboot decided to skip FSP running CPU feature programming. Unfortunately, the assumption of coreboot is not aligned with FSP when it comes to the behaviour of `CpuMpPpi` UPD. FSP assumes ownership of the APs (Application Processors) upon passing `NULL` pointer to the `CpuMpPpi` FSP-S UPD. FSP-S creates its own infrastructure code after seeing the CpuMpPpi UPD is set to `NULL`. FSP requires the CpuMpPei module, file name `UefiCpuPkg/CpuMpPei/CpuMpPei.c`, function name `InitializeCpuMpWorker` to perform those additional initialization which is not relevant for the coreboot upon selecting the SkipMpInit UPD to 1 (a.k.a avoid running CPU feature programming on APs). Additionally, FSP-S binary size has increased by ~30KB (irrespective of being compressed) with the inclusion of the CpuMpPei module, which is eventually not meaningful for coreboot. Hence, this patch selects `MP_SERVICES_PPI_V2_NOOP` config unconditionally to ensure pass a valid pointer to the `CpuMpPpi` UPD and avoid APs getting hijacked by FSP while coreboot decides to set SkipMpInit UPD. Ideally, FSP should have avoided all AP related operations when coreboot requested FSP to skip MP init by overriding required UPDs. TEST=Able to drop CpuMpPei Module from FSP and boot to Chrome OS on Google/Redrix, Kano, Taeko devices with SkipMpInit=1. Without this patch: Here is the CPU AP logs coming from the EDK2 (open-source) [UefiCpuPkg/CpuMpPei/CpuMpPei.c] when coreboot sets `NULL` to the CpuMpPpi UPD. [SPEW ] Loading PEIM EDADEB9D-DDBA-48BD-9D22-C1C169C8C5C6 [SPEW ] Loading PEIM at 0x00076F9A000 EntryPoint=0x00076FA24E2 CpuMpPei.efi PROGRESS CODE: V03020002 I0 [SPEW ] Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE [SPEW ] Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 76FA0239 AP Loop Mode is 2 GetMicrocodePatchInfoFromHob: Microcode patch cache HOB is not found. CPU[0000]: Microcode revision = 00000000, expected = 00000000 [SPEW ] Register PPI Notify: 8F9D4825-797D-48FC-8471-845025792EF6 Does not find any stored CPU BIST information from PPI! APICID - 0x00000000, BIST - 0x00000000 [SPEW ] Install PPI: 9E9F374B-8F16-4230-9824-5846EE766A97 [SPEW ] Install PPI: 5CB9CB3D-31A4-480C-9498-29D269BACFBA [SPEW ] Install PPI: EE16160A-E8BE-47A6-820A-C6900DB0250A PROGRESS CODE: V03020003 I0 With this patch: No instance of `CpuMpPei` has been found in the AP UART log with FSP debug enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8ebe0bcfda513e79e791df7ab54b357aa23d295c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66706 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-02cbfs/vboot: Adapt to new vb2_digest APIJulius Werner
CL:3825558 changes all vb2_digest and vb2_hash functions to take a new hwcrypto_allowed argument, to potentially let them try to call the vb2ex_hwcrypto API for hash calculation. This change will open hardware crypto acceleration up to all hash calculations in coreboot (most notably CBFS verification). As part of this change, the vb2_digest_buffer() function has been removed, so replace existing instances in coreboot with the newer vb2_hash_calculate() API. Due to the circular dependency of these changes with vboot, this patch also needs to update the vboot submodule: Updating from commit id 18cb85b5: 2load_kernel.c: Expose load kernel as vb2_api to commit id b827ddb9: tests: Ensure auxfw sync runs after EC sync This brings in 15 new commits. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-08-31soc/intel/alderlake: Add new pcie5 alias for raptorlakeBora Guvendik
Pcie5_1 is added for DID 0xA72Dh and BDF 0/1/1. References: RaptorLake External Design Specification Volume 1 (640555) BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Id7440bf202d5560ff92807877d48b94054cb1de9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-29soc/intel/alderlake: Rename pcie5 aliasBora Guvendik
Rename pcie5 alias as pcie5_0 since raptorlake is adding a new pcie5 RC. BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Iee669e68e3607b7ffec9f0800e9f0a916defd498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-24soc/intel/adl: Consider INTEL_TME config prior TME MSR programmingSubrata Banik
This patch brings INTEL_TME config check prior programming TME Set Activation Core MSR on all cores. TEST=Able to boot Google/Taeko to OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8af7e305da1050f443929ab33be556e713e53e9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66976 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24soc/intel/alderlake/hsphy: Add support for HSPHY firmware loadingMichał Żygowski
BIOS must send the IP_LOAD HECI command to fetch the firmware for CPU PCIe Gen5 and upload it via CPU REG BAR prior FSP Silicon Init. Implementation based on public Slimbootloader's "Silicon/AlderlakePkg/Library/CpuPcieHsPhyInitLib". TEST=Boot MSI PRO Z690-A and see the HSPHY FW is loaded. PCIe x16 Gen3 GPU card started working in the PCIE 5.0 slot. [DEBUG] HECI: Sending Get IP firmware command [DEBUG] HECI: Get IP firmware success. Response: [DEBUG] Payload size = 0x6944 [DEBUG] Hash type used for signing payload = 0x3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6c6c11581e3d3d9bab0131fae6ef487cafe98080 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-08-22soc/intel/alderlake: Perform TME core activation on all CPUsSubrata Banik
This patch runs `set_tme_core_activate()` on all CPUs (BSP+APs) as per Alder Lake Processor EDS. TEST= Able to build and boot Google/Redrix. Dumping MSR 0x9FF on all logical processors shows zero value being set. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I130480d4fba413d47d0d0137932ec1fb041a88d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66753 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-21soc/intel: Enable TME based on supported CPU SKU and config optionSubrata Banik
This patch removes the static kconfig being used to fill in TME enable FSP UPD. Instead use`is_tme_supported()` and `CONFIG(INTEL_TME)` to check if the CPU has required TME support rather than hardcoding. TEST=FSP debug log shows `TmeEnable` UPD is set appropriately for the TME-supported CPU SKUs. As per FSP-M debug log: Without this CL, Alder Lake-P CPU SKU without TME support: [SPEW ] TmeEnable = 0x1 With this CL, Alder Lake-P CPU SKU without TME support: [SPEW ] TmeEnable = 0x0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8aa2922baaf2a49e6e2762d31eaffa7bdcd43b0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66750 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-21soc/intel: Unravel `INTEL_TME` Kconfig optionAngel Pons
The `INTEL_TME` Kconfig option has a prompt, which means it is meant to be user-configurable. However, it has been selected from Alder Lake and Meteor Lake Kconfig, so `INTEL_TME` cannot be disabled on them. Replace the `select INTEL_TME` statements with default values in order for this option to be user-configurable on all platforms that support it. Change-Id: Ib37c108fcc1004840b82be18fd23c340a68ca748 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66756 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-19soc/intel/alderlake: Add support to skip the MBP HOBV Sowmya
This patch adds the support to enable/disable skipping MBP HOB from the devicetree based on mainboard requirement. Only ADL-N FSP has the required support to skip the MBP HOB and enabling it is saving the Boot time. BUG=b:241850107 TEST=Build and boot to verify that the right value has been passed to the FSP. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Iddeb2c652fac9513b14139d6f732d333bbb989d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-17soc/intel/alderlake/acpi: Changing USB ports indexing.Adam Mills
xhci.asl places the SS ports at 11-14, following HS ports 1-10. However, for Nissa, the kernel detects 12 HS ports 1-12 and 4 SS ports at 13-16, resulting in the PLD intended for SS ports 1 and 2 being associated with HS ports 11 and 12. Changing the asl for SS to 13-16 makes locations associate correctly and peering work. BUG=b:234544025 BRANCH=firmware-brya-14505.B TEST=manually verified on Nissa and Brya devices Change-Id: I57aef771a7ff086b71a9e90b81e1a3635f832b2f Signed-off-by: Adam Mills <adamjmills@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66590 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-16soc/intel/alderlake: Fill ucode loading UPD if USE_FSP_MP_INIT enableSubrata Banik
This patch calls into a helper function to fill `2nd microcode loading FSP UPD` if FSP is running CPU feature programming. TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8534305e4e973c975ad271b181a2ea767c840ae3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66686 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13Revert "soc/intel/alderlake: Enable energy efficiency turbo mode"Jeremy Compostella
This reverts commit 844dcb3725fc95df53a7229703f5059d2c36f98e. A power and performance analysis performed on Alder Lake demonstrated that with an EPP (Energy Performance Preference) at 50% along with EET (Energy Efficient Turbo) disabled, the overall SoC performance are similar or better and the SoC uses less power. For instance some browser benchmark results improved by 2% and some multi-core tests by 4% while at the same time power consumption lowered by approximately 7.6%. BRANCH=firmware-brya-14505.B BUG=b:240669428 TEST=verify that ETT is disabled `iotools rdmsr 0 0x1fc' Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I96a72009aaf96d4237d57f4d5c8b1f41f87174d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66281 Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-12Fix Alder Lake and Raptor Lake Device ID'sMaximilian Brune
- ADP_P_* -> RPP_S_* (got mixed up I guess) - Remove duplicates of ADP_S_ESPI_* - Add infix _ESPI_ to all ADP_S device ID's Document: 619362 Change-Id: Ic18ecbd420fc598f0ef6e3cf38e987ac3ae6067e Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66629 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12Add missing ADL-S device identificationMaximilian Brune
R680E, Q670E, H610E are the ADL-S IoT variants TEST=Boot ADL-S RVP DDR5 and see silicon info is reported as PCH: AlderLake-S R680E Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I1804994b4b72f0484eabb15323736679d2668078 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-12soc/intel/alderlake: Fix DDR5 channel mappingAngel Pons
DDR5 memory modules have two separate 32-bit channels (40-bit on ECC memory modules), and the SPD info refers to one channel: the primary bus width is 32 (or 40) bits and the "DIMM size" is halved. On Alder Lake, there are 2 memory controllers with 4 32-bit channels each for DDR5. FSP has 16 positions to store SPD data, some of which are only used with LPDDR4/LPDDR5. To try to make things less confusing, FSP abstracts the DDR5 channels so that the configuration works like on DDR4. This is done by copying each DIMM's SPD data to the other half-channel. Thus, fix the wrapper parameters for DDR5 accordingly. Tested on AlderLake-P DDR5 RVP (board ID 0x12), both DIMM slots now function properly. Without this patch, only the top slot would work. Change-Id: I5f01cd77388b89ba34d91c2dc5fb843fe9db9826 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Tested-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66608 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-07soc/intel/alderlake: Fix RPL-P 282 15W GT ICC MAXJeremy Compostella
The software used to read the document listing the VR settings turns out to not be perfectly compatible. Indeed, it displays a value of 55A for RPL-P 282 15W GT ICC MAX while the correct value actually is 40A. After a thorough review using the software used to create the document, it is the only value presenting a discrepancy. BRANCH=firmware-brya-14505.B BUG=b:239797178 TEST=build and boot Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Iee293c87a66f0cd32714766e3ad81eee1a411723 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-08-03soc/intel/alderlake: Add config for IoT FSP supportLean Sheng Tan
Add new config FSP_TYPE_IOT to add the IoT FSP option so that respective mainboard Kconfig can use IoT FSP if needed. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I01d891348c039269138e64290ae3d6ec75d3c687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-03soc/soc/intel: Add UFS device with ref-clk-freq propertyMeera Ravindranath
UFS storage devices require the bRefClkFreq attribute to be set to operate correctly in high speed mode. The correct value is determined by what the SoC / board supports. For the ADL UFS controller, it is 19.2 MHz. a) Introduce a new ACPI property "ref-clk-freq". b) Add support to configure this property using an SoC Kconfig. Kernel patch: https://web.archive.org/web/20220801060732/https://lore.kernel.org/all/ 20220715210230.1.I365d113d275117dee8fd055ce4fc7e6aebd0bce9@changeid/ BUG=b:238262674 TEST=Build,boot Nirwen and dump SSDT entries and check that the kernel correctly parses ref-clk-freq as 19.2 MHz. Scope (\_SB.PCI0) { Device (UFS) { Name (_ADR, 0x0000000000120007) // _ADR: Address Name (_DDN, "UFS Controller") // _DDN: DOS Device Name Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "ref-clk-freq", 0x0124F800 } } }) } } Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Reka Norman <rekanorman@chromium.org> Change-Id: I80c338a8a61f161b0feb6c5a3ca00cf5e0cfb36c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-02soc/intel/alderlake: Configure DDR5 Physical channel width to 64Meera Ravindranath
A DDR5 DIMM internally has two channels each of width 32 bit. But the total physical channel width is 64 bit. BUG=b:180458099 TEST=Boot DDR5 to kernel Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: Ic5e9c58f255bdf86a68ce90a4f853bf4e7c7ccfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52730 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-08-02soc/intel/alderlake: Add IRQ constraints for CPU PCIe portsTim Crawford
Copy the constraint from ADL-S to ADL-P. Fixes the following warning in Linux on System76 oryp9, which has an NVIDIA GPU on the bridge. pcieport 0000:00:01.0: can't derive routing for PCI INT A This, in turn, resolves an IRQ conflict with the PCH HDA device that would cause a stack track on every boot. irq 10: nobody cared (try booting with the "irqpoll" option) <snip> [<00000000bf549647>] azx_interrupt [snd_hda_codec] Disabling IRQ #10 Change-Id: I550c80105ff861d051170ed748149aeb25a545db Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66285 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-29soc/intel/alderlake: Add missing TDP and Power Limits for ADL-SMichał Żygowski
Add TDP and Power Limit settings for ADL-S 8+8 150W, 4+0 and 2+0. The System Agent PCI IDs were not present in older 2.1 revision of DOC #619501. Now that the mapping of these IDs to SKUs is known, fill the missing TDPs and Power Limit settings based on DOC #626343. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I23dd8478e60bcc81a1048f2f6e6717dd281d1a69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-29soc/intel/alderlake: Set VccIn Aux Imon IccMax for ADL-S 4+0 and 2+0Michał Żygowski
Add missing System Agent PCI IDs for ADL-S 4+0 and 2+0 to configure VccIn Aux Imon IccMax. They were not present in older 2.1 revision of DOC #619501. Based on DOC #619501 rev 2.6. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Idfd57ce9b63db5d5fcc9d4efb8aa27ed7cc6222d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-29soc/intel/alderlake/vr_config.c: Add VR params for ADL-SMichał Żygowski
Based on DOC #619501, #634885, #626343. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib50db521e4d127a773f903b45d4bec5c5cc180d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-28soc/intel/alderlake: Add support for more CPU PCIe RP UPDsTim Wawrzynczak
There are 3 more CPU PCIe RP UPDs that are the current code is not setting, and some boards may want to set these, so this patch adds support to set these UPDs. The default values for any existing boards using these UPDs should not change with this patch. The UPDs are: - CpuPcieRpDetectTimeoutMs - CpuPcieRpAspm - CpuPcieRpSlotImplemented Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Id48019f984e8e53ff3ce0c3c23e02dab65112c99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66197 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-28soc/intel/alderlake: Enable LPIT supportJeremy Soller
Add SLP_S0 residency register and enable LPIT support. Change-Id: I45e1fc9df3e782cdaac810af3189c5797b1fe413 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-28soc/intel/alderlake: Set Energy Perf Bias appropriate default valueJeremy Compostella
The current "normal" EPB (six) setting resulted in the desired out of box power and performance for several CPU generations. However, a power and performance analysis on Alder Lake and Raptor Lake CPUs demonstrates that this value results in undesirable higher uncore power and that seven is a more appropriate value. Note: the Linux kernel "4ecc933b x86: intel_epb: Allow model specific normal EPB value" patch sets the EPB to 7 for Alder Lake. BRANCH=firmware-brya-14505.B BUG=b:239853069 TEST=verify that EPB is set by coreboot Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I5784656903d4c58bedc5063ee3ef310a99711050 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66059 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-28soc/intel/alderlake: Enable Energy/Performance Bias controlJeremy Compostella
According to document 619503 ADL EDS Vol2, bit 18 of MSR_POWER_CTL must be set to be able to set the Energy/Performance Bias using MSR IA32_ENERGY_PERF_BIAS. Note that since this bit was not set until this patch, the `set_energy_perf_bias(ENERGY_POLICY_NORMAL);' call in `soc_core_init()` was systematically failing. BRANCH=firmware-brya-14505.B BUG=b:239853069 TEST=verify that EPB is set by coreboot Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Ic24abdd7f63f4707b8996da4755a26be148efe4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-23soc/intel/alderlake: Hide PMC and IOM devicesJeremy Soller
Hide these ACPI device so Windows does not warn about missing device drivers. Change-Id: Iba6cf7a17eefc9f4f247621f6625151f2fd5f3a7 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-20soc/intel/alderlake/fsp_params.c: Set DdrSpeedControl UPDFranklin Lin
When override "max_dram_speed_mts", set the DdrSpeedControl to manual. (0:Auto, 1:Manual) BUG=b:229549930 BRANCH=none TEST=build coreboot without error Signed-off-by: Franklin Lin <franklin_lin@wistron.corp-partner.google.com> Change-Id: Iffbbee8082fb1a41e0ed1db3f4ea9ec4709c9ce7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65877 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20soc/intel/common/pch: Decouple CLIENT from BASEAngel Pons
In preparation to add a third option, have "Client" platforms select a dedicated Kconfig option instead of the common "_BASE" option. Rewrite the help texts to clarify what "Client" and "Server" mean, because the terms refer to the type of silicon and not to the market segment. Some uniprocessor (single-socket) servers are actually client platforms and there are some multi-socket workstations based on a server platform. Change-Id: I646729d709f60ca2b5e74df18c2b4e52f9b10e6b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-14soc/intel/alderlake: Support PCIe hardware compliance test modeSridahr Siricilla
The validation process verifies that hardware components comply with the standard hardware specifications. For instance, PCI express implementation must comply with the hardware PCIe specification requirements: Electrical, Configuration, Link Protocol and Transaction Protocol. To perform these tests the hardware must be configured in a particular state: some feature related to power management need to be turned off, hot plug should be enabled... This patch sets the appropriate FSP Updateable Product Data flags to get the hardware in the proper configuration: - Enable PCIe hotplug on all ports - Set clock sources to run free - Set the FSP compliance test mode flag BUG=b:235863379 TEST=Compilation with and without the flag Verify code path with instrumentation Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Ic07b9276121dfbd273a8f63a1f775ddbd3566884 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-08soc/intel/alderlake: Hook-up public Alder Lake microcodeMichał Żygowski
CPUIDs and Engineering Samples decoding based on DOC #618427. Keep MICROCODE_BLOB_UNDISCLOSED for PCH-N SKUs as microcode blobs are still missing. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ibb1337e5cbf5b82fdaceb7eb4661d708a32ff0ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/65564 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-07-08soc/intel/adl: Add support to configure package c-state demotionV Sowmya
This patch adds the support to enable/disable package c-state demotion feature from the devicetree based on mainboard requirement. BUG=b:235005582 TEST=Build and boot to verify that the right value has been passed to the FSP. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I9e254988bc3d20b9f9e42a605cc0ebd419ab49ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/65663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-07soc/intel/alderlake: change functions arguments to constEran Mitrani
Change-Id: Ib8d9a9e94d16ad291d9cc8576db845a634ae026e Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65614 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07soc/intel/alderlake/acpi/gpio.asl: Add GPIO Commnity 3 for ADL-SMichał Żygowski
This patch fixes the issue with INTC1056 invalid resource reported by alderlake-pinctrl Linux driver on ADL-S platform. The driver also includes GPIO Community 3 in the GPIO list compared to ADL-N which was missing in GPIO ACPI device. TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A DDR4 WIFI and check there is no invalid resource error reported by alderlake-pinctrl Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I23da68c247de86438cc2eef2b5a5a9aa711c1d7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-07soc/intel/alderlake/acpi/gpio.asl: Fix lower case typoMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If66c2799d4d74ff9f309665a0336b5f679796f9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-06soc/intel/alderlake: Add check for CSE FW sync in romstageKrishna P Bhat D
Some Alder Lake-N boards will use compressed ME RW blobs to obtain savings on the SPI size (1916KB before compression, ~1132KB after compression). So add an additional check before calling cse_fw_sync() from romstage. When compressed blobs are used, the call to CSE firmware update has to be in post-RAM stages. BRANCH=firmware-brya-14505.B Change-Id: I0d9ede52cb493974e4ba6e2e2cf11c9789b3b087 Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63760 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-04soc/intel/alderlake: RPL-P power limits and VR settingsJeremy Compostella
This patch sets the Power Limits and Voltage Regulator settings for three RaptorLake SKUs (45W, 28W and 15W) following the guidance from document 686872 (June 7th edition). BUG=b:237809660 TEST=Power Limit and VR serial logs review + debug instrumentation SKUs successfully booted Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I7e9d4039615e6c33b869c6243efbfeb2259ac219 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65582 Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-04soc/intel/alderlake: remove unnecessary test conditionJeremy Compostella
mch_id is set to zero and then unnecessarily tested. TEST=build and boot image on ADL RVP board Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I4f48742b04edd50fbc0db342b563534e709d6fdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-04soc/intel/alderlake/fsp_params.c: Handle CnviWifiCore parameterMichał Żygowski
Platform with public FSP hooked-up have an additional parameter to control CNVi WiFi with CnviWifiCore UPD. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I19efb645fbe1530a571c92d0573c1c60ff6605a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-04soc/intel/alderlake: Hook up ADL-P and ADL-S public FSPMichał Żygowski
Update 3rdparty/fsp submodule to include AlderLake FSP. Hook up the Kconfig settings to point to Fsp.fd and headers for ADL-S and ADL-P platforms which the FSP has been published for. The FSP binaries are compliant with the specification revision 2.3 so update these settings accordingly. Although FSP header is v2.3 compliant, the features set of the FSP v2.3 is not being met. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I577931da7952b681534bb78b7b2c7683cd99febd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65519 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30soc/alderlake: Enable all bits for IO decode / enable registerSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I86423c45ca33a79d3d8cf8e4ca4737da94a4aa4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-06-30soc/intel/alderlake: Add BUILDING_WITH_DEBUG_FSPKangheui Won
Intel FSP has "debug" build which is not public, used for debugging by approved developers. Add a Kconfig to indicate that coreboot is building with debug version of FSP so we can adjust few things (i.e. flash layout) in the case. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ibc561498d7edcb9d7ec155f090822f1eb25d10cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65466 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-30soc/intel/alderlake: add chipset devicetree for ADL-SMichał Kopeć
Add chipset devicetree and power limits for AlderLake-S platform. Based on Intel docs #619501, #619362 and #626343. Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2022-06-30soc/intel/alderlake: Add ADL-S PCI IRQ constraintsMichał Żygowski
Add ADL-S specific table with IRQ constraints to avoid accessing non-existent devices. Also when using debug FSP, silicon init would assert on assigning IRQs for non-existent devices. This patch fixes the problem. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib4464a85bc11a8603bf471ea348bbfc9481db4aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-30soc/intel/alderlake/iomap: Correct the ADL-S reserved rangeMichał Żygowski
Due to incorrectly interpreted DOC #630603, the reserved range remains the same for all ADL platforms and is sync with src/soc/intel/common/block/acpi/acpi/northbridge.asl which defines the range as 0xfc800000-0xfe7fffff. The range 0xfe000000-0xfe7fffff was only mean for static allocations, but the rest is also reserved. The only difference between ADL-S and other ADL platforms is Trace Hub base. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I9b1f79cc351de422acf182c27870c29dbe57fe4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-28soc/intel: Add Raptor Lake device IDszhixingma
Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs. References: RaptorLake External Design Specification Volume 1 (640555) 600/700 Series PCH External Design Specification Volume 1 (626817) BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=Booted to OS on adlrvp + rpl silicon Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I8e8b9ec6ae82de7d7aa2302097fc66f47b782323 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65117 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-28soc/intel/alderlake/fsp_params.c: Fill PCI SSID parametersMichał Żygowski
Code taken from TGL base. TEST=Boot MSI PRO Z690-A WIFI DDR4 and see all devices have SSID applied Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3a6d299ec40bac8e29d06926572e375d7d835e29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-28soc/alderlake: Add ADL-S PCIe supportMichał Żygowski
Extend the code to support ADL-S PCIe Root Ports. Based on DOC #619362 and #619501. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ibb57ad5b11684c0079e384d9a6ba5c10905c1a23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63654 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-28soc/intel/alderlake/acpi: Add ADL-S devicesMichał Żygowski
Add PCIe Root Ports, USB ports and SIO devices for ADL-S chipset. Add IRQ routing tables for PCIe Root ports up to 28th. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I508fa1396b07f38801bcf50cdfdc876356d7ae9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63785 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-27soc/intel/*/Kconfig: Fix typo in commentAngel Pons
clcok ---> clock Change-Id: Ie41524f6500479162984fa9050d942f4e295f00a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-27soc/intel/alderlake: Implement MultiPhase SI Init Index 2 callbackSubrata Banik
The details about how the CPU multiprocessor init (MP) has migrated from coreboot to FSP can be found in https://doc.coreboot.org/soc/intel/mp_init/mp_init.html. The major reason behind this migration is to support the Intel proprietary and restricted CPU feature programming which can't be performed if coreboot sets the BIOS_DONE or BIOS Reset CPL as part of coreboot MP Init flow (prior to calling FSP-S). Hence, the new flow introduced with Tiger Lake platform forced having monolithic MP Init peformed by FSP (using coreboot MP PPI wrapper code). The last 3-4 years of FSP doing MP Init has demonstrated ample issues during platform bringup which is specific to UEFI MP Service implementation and not relevant to open source coreboot. This new flow makes the debug and validation aspect complicated where any FSP MP Init code changes should have been validated with coreboot MP PPI wrapper else might cause some failure, unfortunately, the validation commitment has never been met, hence, issue debugging is the only solution that remains in practice. Most importantly, the restricted feature programming which demanded closed source MP Init (for features like SGX and C6DRAM) has never been enabled in coreboot (starting with Alder Lake, the SGX feature has been dropped). This patch attempts to decouple FSP-S doing MP Init from the rest of the FSP-S silicon init and introduces 2nd MultiPhase SI init which allows bootloader to perform the mandatory SoC programming before FSP-S has done with PM programming (a.k.a set the reset CPL). The core/uncore BWG suggests the minimum SoC programming before BIOS Reset CPL is set. coreboot uses the MultiPhaseSI Init Index 2 to perform the required CPU programming before enabling the BIOS Reset CPL. This implementation would allow us to get rid of FSP running CPU feature programming and additionally make several EDK2 MP service modules optional (those are packed to create FSP-S blob). In summary, this change would allow coreboot to utilize open source MP init without running into FSP-S related code blocks. Note: At present, Intel Alder Lake FSP doesn't have support for MultiPhase SI Init, Index 2 (submitted a FSP code changes over chrome-internal to enable this feature to decouple MP Init from FSP-S init). BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Perform several thousands cycles of suspend test and power cycle without running into any issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I314c63c917ef6fdd32f364b2c60bae22486b8b74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64979 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-26soc/intel/alderlake: Drop debug interface selectionSubrata Banik
This patch drops FSP Debug interface selection as coreboot now decides the UART inerface to redirect the debug msg. BUG=none TEST=Able to see all coreboot and FSP debug log with and without this patch. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If8c07d7e63c5d445fdb77ac38b99217bf015e15f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-23soc/intel/adl: Cast size in systemagent.c to fix overflowEran Mitrani
This CL fixes my previous CL (commit ca741055e) which introduced a couple of issues found by Coverity (see below). The Coverity explanation is: "Potentially overflowing expression "size_field * 1048576U" with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned)." *** CID 1490122: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /src/soc/intel/alderlake/systemagent.c: 305 in get_dpr_size() *** CID 1490121: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /src/soc/intel/alderlake/systemagent.c: 254 in get_dsm_size() BUG=b:149830546 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage' builds correctly. Tested on an Anahera device which successfully boots to ChromeOS with kernel version 5.10.109-15688-g857e654d1705. Change-Id: Ib2d66ad24a5ad67b51036ad376a6938f698134c3 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65212 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-23soc/intel/alderlake/romstage: Add desktop UserBd optionsMichał Żygowski
Add the desktop board types as per DOC #573387. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8cca98f0fac51e537b472958ee602e116b48f6d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-06-23soc/intel/alderlake: Fix PRMRR resource range calculation issueSubrata Banik
This patch fixes an issue introduced with commit ca741055e (soc/intel/adl: Add missing claimed memory regions) where PRMRR base should be read using MSR 0x2a0 and mask from MSR 0x1f5 instead System Agent PCI configuration space. With this change, coreboot is able to read PRMRR base when the PRMRR size > 0. TEST=Able to read PRMRR base MSR 0x2a0 in proper with this CL. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3770b1a92dbd2552cf1b9764522c9cac9f29c13c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eran Mitrani <mitrani@google.com>
2022-06-22soc/intel/alderlake: add GPIO definitions for PCH-SMichał Kopeć
Add GPIO definitions for ADL-S, similarly to how TGL/TGL-H handles the split. Based on: - Intel PCH-S EDS Vol2 (#621483) - Alderlake-S FSP - slimbootloader sources - Linux alderlake-pinctrl driver Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-22soc/intel/alderlake: Remove menu option for MAX_PCIE_CLOCK_SRCCliff Huang
MAX_PCIE_CLOCK_SRC is not an user-configurable option. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: Ia49f6e236e8853c377e9096500d96f21dbdc9b8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65298 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/intel/alderlake: Allow possible options for MP InitSubrata Banik
This patch creates choice that lists all possible options to perform MP Init as below: 1. USE_FSP_MP_INIT: Allow coreboot to bring APs from reset and FSP runs feature programming based and selects MP_SERVICES_PPI_V2 config. 2. USE_COREBOOT_MP_INIT: Allow coreboot to perform MP Init (both AP init and feature programming) using native implementation. Additionally, selects required RELOAD_MICROCODE_PATCH when coreboot is expected to run MP Init. Refactor SoC code to allow required FSP UPD override based on selected MP Init option. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I20adc1935890c4c6bcd11fd086838f15d0723932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64977 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20soc/intel/alderlake/chip.c: Add missing ADL-S USB ports ACPI namesMichał Żygowski
ADL-S has more USB ports than mobile chipsets. Add missing ACPI names. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ice5f7784f9de0364681be00fc5cc445caf9d1b3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63655 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-18soc/intel/alderlake: Skip PCIe source clock assignment if incorrectCliff Huang
When an enabled root port without pcie_rp clock being specified, the empty structure provides invalid info, which indicates '0' is the clock source and request. If a root port does not use clock source, it should still need to provide pcie_rp clock structure with flags set to PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it is considered that pcie_rp clock structure is not provided for that root port. Add check and skip for enabled root port that does not have clock structure. In addition, a root port can not use a free running clock or clock set to LAN. Note that ClockUsage is either free running clock, LAN clock, or the root port number which consumes the clock. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I17d52374c84ec0abf888efa0fa2077a6eaf70f6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-17soc/intel/{alderlake, common}: Rename the pre_mem_ft structureSridhar Siricilla
The patch renames identifiers (macros, function and structure names) in the basecode/debug/debug_feature.c to generic names so that they can be used to control the features which may have to be controlled either during pre and post memory. Currently, the naming of identifiers indicate that it meant to control the features which can be controlled during only pre-memory phase. TEST=Build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I53ceb25454027ab8a5c59400402beb6cc42884c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-17soc/intel/alderlake/report_platform.c: Add ADL-S identificationMichał Żygowski
Based on DOC #619501, #619362 and #618427 TEST=Boot MSI PRO Z690-A DDR4 WIFI and see the silicon info is reported as ADL-S. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8051113515ef63fc4687f53d25140a3f55aadb6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-16soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-SMichał Żygowski
Alder Lake-S CPUs do not have TCSS and USB4 devices. Unselect them. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ifc643d440107754dfe1a0844964f70de670cb1f1 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-16soc/intel/alderlake/fsp_params.c: Add VccIn Aux Imon IccMax for ADL-SMichał Żygowski
Based on DOC #619501. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia95404e717787edbdb67c9e584e749526b973427 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15soc/intel/adl: Add missing claimed memory regionsEran Mitrani
The Alder Lake chipset has several more reserved memory regions that are unavailable to the resource allocator than are currently marked as such in the system agent code. This CL adds the following regions (documented in Intel docs #626540, #619503): 1. TSEG 2. GSM 3. DSM 4. PCH_RESERVED 5. CRAB_ABORT 6. APIC 7. TPM 8. LT_SECURITY Claimed regions before this change: ======================================================== base 0 size a0000 // 0 - > 0xa0000 base a0000 size 20000 // legacy VGA base c0000 size 40000 // RAM base c0000 size 76f40000 // 0xc0000 -> top_of_ram base 77000000 size 9400000 // top_of_ram -> TOLUD base c0000000 size 10000000 // PCIEXBAR base f8000000 size 2000000 // MMSPI base fb000000 size 1000 // REGBAR base fed80000 size 4000 // EDRAMBAR base fed84000 size 1000 // TBT0BAR base fed85000 size 1000 // TBT1BAR base fed86000 size 1000 // TBT2BAR base fed87000 size 1000 // TBT3BAR base fed90000 size 1000 // GFXVTBAR base fed91000 size 1000 // VTVC0BAR base fed92000 size 1000 // IPUVTBAR base feda0000 size 1000 // DMIBAR base feda1000 size 1000 // EPBAR base fedc0000 size 20000 // MCHBAR base 100000000 size 17fc00000 // 4GiB -> TOUUD Claimed regions with this change: ======================================================== base 0 size a0000 // 0 - > 0xa0000 base a0000 size 20000 // legacy VGA base c0000 size 40000 // RAM base c0000 size 76f40000 // 0xc0000 -> top_of_ram base 77000000 size 9400000 // top_of_ram -> TOLUD base 7b800000 size 800000 // TSEG base 7c000000 size 800000 // GSM base 7c800000 size 3c00000 // DSM base c0000000 size 10000000 // PCIEXBAR base f8000000 size 2000000 // MMSPI base fb000000 size 1000 // REGBAR base fc800000 size 2000000 // PCH_RESERVED base feb00000 size 80000 // CRAB_ABORT base fec00000 size 100000 // APIC base fed40000 size 10000 // TPM base fed50000 size 20000 // LT_SECURITY base fed80000 size 4000 // EDRAMBAR base fed84000 size 1000 // TBT0BAR base fed85000 size 1000 // TBT1BAR base fed86000 size 1000 // TBT2BAR base fed87000 size 1000 // TBT3BAR base fed90000 size 1000 // GFXVTBAR base fed91000 size 1000 // VTVC0BAR base fed92000 size 1000 // IPUVTBAR base feda0000 size 1000 // DMIBAR base feda1000 size 1000 // EPBAR base fedc0000 size 20000 // MCHBAR base 100000000 size 17fc00000 // 4GiB -> TOUUD BUG=b:149830546 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage' builds correctly. Tested on an Anahera device which successfully boots to ChromeOS with kernel version 5.10.109-15688-g857e654d1705. Also ran dmseg, and saw the added regions in e820 prints. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I058a5c1cc59703e35ceddb8a7e26fb22a6a2b75e Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-15soc/intel/alderlake: remove unnecessary test conditionJeremy Compostella
mch_id is set to zero and then unnecessarily tested. TEST=build and boot image on ADL RVP board Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I20734e1638714027b976043b3a0457cbf3cd8442 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65121 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15soc/intel/alderlake: remove unnecessary MSR definitionJeremy Compostella
MSR_VR_MISC_CONFIG2 is not used by AlderLake code. TEST=compilation check Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/65120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-06-15soc/intel/alderlake/Kconfig: Unselect IPU for ADL-SMichał Żygowski
Alder Lake S CPUs do not have IPU device. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I79b084273f407119d903ed6f0cadf0084e8dda6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-10soc/intel/alderlake: Add Kconfig for Raptor LakeBora Guvendik
Until FSP for RPL and ADL align, mainboards using RPL should select SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together. Currently, ADL FSP headers and RPL FSP headers differ. Use RPL FSP header with Raptor Lake silicon. This code can be removed once ADL and RPL start using the same FSP. BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Iaf95352b9cafb81f23522bcf63753d199c0420eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-09soc/intel/alderlake: Drop enable_bios_reset_cpl() functionSubrata Banik
This patch drops enable_bios_reset_cpl() as FSP sets the BIOS Reset CPL before performing Graphics PM init (as part of FSP-S), hence, enable_bios_reset_cpl() function getting called inside systemagent.c is meaningless. Also, drop 1ms delay after setting the BIOS reset CPL. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I87beb444d3910f212a5a627cb449031db6cae38d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64837 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09soc/intel/alderlake: Add config option for S3 ACPISean Rhodes
Add Kconfig option `SOC_INTEL_ALDERLAKE_S3` which will adjust the ACPI to not offer D3Cold when using S3. This patch is the Alder Lake equivalent of CB:59024. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I04df8e106f9d53337b9eb5d2b9041b44a0e36684 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-09soc/intel/alderlake: add support for external source clockCliff Huang
Support up to 10 PCIe source clock out, including source clock out 7, 8, 9. This allows boards to use source clock 7, 8, 9. BUG=b:233252409 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63943 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-09soc/intel/alderlake: Add support for PCIe slot & device detect timeoutCliff Huang
1. add timeout for root port detection and pass to FSP. 2. add 'slot implemented' flag and pass to FSP. 3. PcieRpSlotImplemented needs to be set when the root port is set to hotplug. There is an assertion in FSP checking this. 4. PcieRpSlotImplemented is updated only when it is built-in as it is default to slot implemented in FSP. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-04soc/intel: Rename heci_init to cse_initSubrata Banik
This patch renames heci_init() to cse_init() as HECI initialization should have a bigger scope than just initializing the CSE (a.k.a HECI1 alone). BUG=none TEST=Able to build and boot google/taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic7edd55ccdcd70b244615fa06f81803a0ae6ce80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-02soc/intel/alderlake: add power limits for Alder Lake-N SKUsVidya Gopalakrishnan
This patch adds support for the ADL-N SKUs based on the PCH ID. Document reference: 645548 (ADL-N EDS Volume 1). BUG=None BRANCH=None TEST=Build FW and test on adln_rvp board Change-Id: I24c18a27a4a2c68c78bc3dc728c45ba04f57205d Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64472 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-06-02soc/intel/common/cpu: Use SoC overrides to set CPU privilege levelSubrata Banik
This patch implements a SoC overrides to set CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4584516102560e6bb2a4ae8c0d036be40ed96990 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-05-26soc/intel/alderlake: Hook up FSP hyper-threading setting to option APIFelix Singer
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Change-Id: I520a936b4c3a8997ba2c6bea0126b3bbcc5d68ce Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-25soc/intel/alderlake: Add chip config for DPA PreWakeleo.chou
The FSP includes a UPD to set the DPA (Dynamic Periodicity Alteration) PreWake value, which can be used to set the maximum pre-wake randomization time in "micro-ticks". This patch adds support for configuring that value. BUG=b:228410327 TEST=build FW and checked DPA value by fsp log. Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I08897c590a88aba058cb9e364185ea0794e1e7c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-24soc/intel/alderlake: Drop unused `PCH_DEV_SLOT_LPC` macroSubrata Banik
This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the Alder Lake SoC PCI device list. BUG=none TEST=Able to build and boot taeko, google board. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib2ae40fcc4499de34534f27f03b4c359c37409e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-18soc/intel/alderlake: Add support enable external V1P05/Vnn railsV Sowmya
This patch adds the support to enable the external V1P05/Vnn rails in S0 state via devicetree. BUG=b:223102016 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I555e5607af15a5f5d83ef74321b1b71f17cca289 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-18soc/intel/alderlake: Update the VccIn Aux Imon IccMaxV Sowmya
This patch updates the VccIn Aux Imon IccMax for ADL-N to SOC SKU specific value of 27A. Kit: 646929 - ADL N Platform Design Guide BUG=b:223102016 TEST=Verified that VccIn Aux Imon IccMax value is set to 27mA. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: If09cd1112fac9b30ff04c45aa5a6062c2513c715 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-18soc/intel/alderlake: Configure the SKU specific parameters for VR domainsV Sowmya
This patch configures the SKU specific power delivery parameters for the VR domains for ADL-N. +--------------+-------+-------+-------+-------+-----------+--------+ | SKU |Setting| AC LL | DC LL |ICC MAX|TDC Current|TDC Time| | | |(mOhms)|(mOhms)| (A) | (A) | (msec)| +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 081 | IA | 4.7 | 4.7 | 53 | 22 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 29 | 22 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 081(7W) | IA | 5.0 | 5.0 | 37 | 14 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 29 | 14 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 041(6W) | IA | 5.0 | 5.0 | 37 | 12 | 28000 | + Pentium +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 29 | 12 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 041(6W) | IA | 5.0 | 5.0 | 37 | 12 | 28000 | + Celeron +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 26 | 12 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-N 021(6W) | IA | 5.0 | 5.0 | 27 | 10 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 6.5 | 6.5 | 23 | 10 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ Kit: 646929 - ADL N Platform Design Guide -> Power_Map_Rev1p0 BUG=b:223102016 TEST=Boot and verify the UPD values are configured properly for ADL-N SKU's. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I3d6ae20323d3e859f52228822d4cbad143921a37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-16soc/intel: Add Raptor Lake device IDsBora Guvendik
Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs. References: RaptorLake External Design Specification Volume 1 (640555) 600/700 Series PCH External Design Specification Volume 1 (626817) Change-Id: I39e655dec2314a672ea63ba90d8bb3fc53bf77ba Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
2022-05-16soc/intel/*: Fix up header guardsArthur Heymans
Change-Id: If9ae375629c8af3d32b4c5493b5d63203e8847aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-16soc/intel/*: Use SSDT to pass A4GB and A4GSArthur Heymans
GNVS is more fragile as you need to keep struct elements in sync with ASL code. Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-16soc/inte/*/gpio; Add GPE_EN and GPE_STS register definitionMaulik V Vaghela
coreboot needs to set GPE_EN bit for the GPIOs which are wake capable from s0ix/sleep. Due to GPIO locking mechanism, coreboot/OS will not be able to write GPE_EN register post GPIO has been locked. This patch adds support in SoC code to provide correct offset for GPE_EN and GPE_STS registers to the common code. Plan is to use this offsets to set GPE_EN bits before GPIO locking in coreboot which will be part of subsequent CL. BUG=b:222375516 BRANCH=firmware-brya-14505.B TEST=Check if code compiles for Brya and correct offset values are printed. Change-Id: I6b813b30b8b360f8eccbf539b57387310e380560 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-15soc/intel/alderlake: Move array declarationArthur Heymans
Clang does not like array declarations inside plain switch cases. There are 2 options to fix this: use a block inside the switch statement, or declare it outside the switch statement. This does the latter. Change-Id: I9a02136fd63ac171b2bec4647c30c7eece930246 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-14soc/intel/alderlake: Fix Coverity CID 1488814Tarun Tuli
CID 1488814:  Uninitialized variables  (UNINIT) Commit c66ea98 introduced an issue after static analysis on merge. Because every APIC is associated with a CPU, this did not result in any issues at runtime but should be fixed/cleaned up. Now, the path name is initialized to null. Fixes: Coverity CID 1488814, commit c66ea98 TEST=Built on brya Change-Id: I0cfc8fd7a0c39e6610a9361630e3755293084f3d Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-13soc/intel/alderlake: Use correct formatted print for size_tArthur Heymans
Change-Id: Ifc0374ed49ecefc57dec8e72e73bac031838a9f5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64238 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12soc/intel/alderlake: provide a list of D-states to enter LPMTarun Tuli
Implement sub-function 1 (Get Device Constraints) of the Low Power S0 Idle Device-Specific Method (_DSM). This provides a way in which to describe various devices required D-states to enter LPM (S0ix). The information can be used to help in diagnostics and understanding of S0ix entry failure. Values were derived from Intel document 595644 (rev 0.45) and the ADL FSP sample ASL. This implementation adds support for ADL. Other SoC's could be ported to be included as well. If they aren't, they will default to the existing behavior of a single hardcoded device to ensure compatibility with Windows. TEST=Built and tested on brya by verifying SSDT contents Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao
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