diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-06-20 23:03:16 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-06-23 15:13:05 +0000 |
| commit | 964a70e998fd4b29d7df48d12a5dd51610043a3e (patch) | |
| tree | 0146ee23e0784a24c307eda41f567e92804a4da6 /src/soc/intel/alderlake | |
| parent | e7a68244df92c6194929137e2f4578ef2e328291 (diff) | |
soc/intel/alderlake: Fix PRMRR resource range calculation issue
This patch fixes an issue introduced with commit ca741055e
(soc/intel/adl: Add missing claimed memory regions) where PRMRR base
should be read using MSR 0x2a0 and mask from MSR 0x1f5 instead
System Agent PCI configuration space.
With this change, coreboot is able to read PRMRR base when the
PRMRR size > 0.
TEST=Able to read PRMRR base MSR 0x2a0 in proper with this CL.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3770b1a92dbd2552cf1b9764522c9cac9f29c13c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/systemagent.c | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c index 170c56b71c..05de0ccfbe 100644 --- a/src/soc/intel/alderlake/systemagent.c +++ b/src/soc/intel/alderlake/systemagent.c @@ -8,6 +8,7 @@ #include <arch/ioapic.h> #include <console/console.h> +#include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> #include <delay.h> @@ -78,6 +79,17 @@ static void set_mmio_resource( resource->description = description; } +int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base, + uint64_t *prmrr_mask) +{ + msr_t msr; + msr = rdmsr(MSR_PRMRR_BASE_0); + *prmrr_base = (uint64_t) msr.hi << 32 | msr.lo; + msr = rdmsr(MSR_PRMRR_PHYS_MASK); + *prmrr_mask = (uint64_t) msr.hi << 32 | msr.lo; + return 0; +} + /* * SoC implementation * @@ -112,9 +124,13 @@ void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt) /* PMRR */ size = get_valid_prmrr_size(); if (size > 0) { - uint64_t mask = pci_read_config32(dev, MSR_PRMRR_PHYS_MASK); - base = pci_read_config32(dev, MSR_PRMRR_PHYS_BASE) & mask; - set_mmio_resource(&(cfg_rsrc[count++]), base, size, "PMRR"); + uint64_t mask; + if (soc_get_uncore_prmmr_base_and_mask(&base, &mask) == 0) { + base &= mask; + set_mmio_resource(&(cfg_rsrc[count++]), base, size, "PMRR"); + } else { + printk(BIOS_ERR, "SA: Failed to get PRMRR base and mask\n"); + } } /* GSM */ |