diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-08-12 18:12:46 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-08-16 19:17:06 +0000 |
| commit | fad1cb062e29c5e3a5bcfb6b67c3ce01ed765254 (patch) | |
| tree | a6348ad608b8d442995813b9201637054abd5373 /src/soc/intel/alderlake | |
| parent | a3214c6d763f194b766b967720e7a02d0bfdccdc (diff) | |
soc/intel/alderlake: Fill ucode loading UPD if USE_FSP_MP_INIT enable
This patch calls into a helper function to fill `2nd microcode loading
FSP UPD` if FSP is running CPU feature programming.
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8534305e4e973c975ad271b181a2ea767c840ae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66686
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 1e1f61077e..6826306c12 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -564,7 +564,7 @@ static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg, s_cfg->SerialIoUartMode[i] = config->serial_io_uart_mode[i]; } -static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, +static void fill_fsps_microcode_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { const struct microcode *microcode_file; @@ -581,9 +581,18 @@ static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; } } +} +static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_alderlake_config *config) +{ if (CONFIG(USE_FSP_MP_INIT)) { /* + * Fill `2nd microcode loading FSP UPD` if FSP is running CPU feature + * programming. + */ + fill_fsps_microcode_params(s_cfg, config); + /* * Use FSP running MP PPI services to perform CPU feature programming * if Kconfig is enabled */ |